u-boot-imx-20230503
------------------- - Fixes for : pico-imx6ul, smegw01 - new boards: DMSSE20, Reform 2 - fix: get_boot_device, PLL video rate CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/16211 -----BEGIN PGP SIGNATURE----- iG0EABECAC0WIQS2TmnA27QKhpKSZe309WXkmmjvpgUCZFJGmw8cc2JhYmljQGRl bnguZGUACgkQ9PVl5Jpo76ZirwCggyjQaqPg7dm0OAzfgD2gEoR/058AoI9jLtVd JaM9K5RoIu0V1AjBKXQe =l+ri -----END PGP SIGNATURE----- Merge tag 'u-boot-imx-20230503' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20230503 ------------------- - Fixes for : pico-imx6ul, smegw01 - new boards: DMSSE20, Reform 2 - fix: get_boot_device, PLL video rate CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/16211
This commit is contained in:
Tom Rini
commit
2440719d25
37 changed files with 3162 additions and 60 deletions
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@ -961,6 +961,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \
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fsl-imx8qm-apalis.dtb \
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fsl-imx8qm-mek.dtb \
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imx8qm-cgtqmx8.dtb \
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imx8qm-dmsse20-a1.dtb \
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imx8qm-rom7720-a1.dtb \
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fsl-imx8qxp-ai_ml.dtb \
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fsl-imx8qxp-colibri.dtb \
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11
arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
Normal file
11
arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
Normal file
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@ -0,0 +1,11 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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#include "imx8mq-u-boot.dtsi"
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&pinctrl_uart1 {
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bootph-pre-ram;
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};
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&uart1 { /* console */
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bootph-pre-ram;
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};
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397
arch/arm/dts/imx8qm-dmsse20-a1.dts
Normal file
397
arch/arm/dts/imx8qm-dmsse20-a1.dts
Normal file
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@ -0,0 +1,397 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2017-2018 NXP
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* Copyright 2019-2023 Kococonnector GmbH
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*/
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/dts-v1/;
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/* First 128KB is for PSCI ATF. */
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/memreserve/ 0x80000000 0x00020000;
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#include "fsl-imx8qm.dtsi"
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#include "imx8qm-u-boot.dtsi"
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/ {
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model = "Advantech iMX8QM DMSSE20";
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compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
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aliases {
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mmc0 = &usdhc1;
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mmc2 = &usdhc3;
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};
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chosen {
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bootargs = "console=ttyLP0,115200 earlycon";
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stdout-path = &lpuart0;
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};
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reg_usb_otg1_vbus: usb_otg1_vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb_otg1_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usdhc2_vmmc: usdhc2_vmmc {
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compatible = "regulator-fixed";
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regulator-name = "sw-3p3-sd1";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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imx8qm-mek {
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pinctrl_hog: hoggrp {
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fsl,pins = <
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SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000048
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>;
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};
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0
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SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020
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SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
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SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060
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SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060
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SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060
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SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060
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SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060
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SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060
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SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060
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SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060
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SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060
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SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060
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SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060
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SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060
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>;
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};
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pinctrl_fec2: fec2grp {
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fsl,pins = <
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SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0
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SC_P_ENET1_MDC_CONN_ENET1_MDC 0x06000020
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SC_P_ENET1_MDIO_CONN_ENET1_MDIO 0x06000020
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SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060
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SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060
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SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060
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SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060
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SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060
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SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060
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SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060
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SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060
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SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060
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SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060
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SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060
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SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060
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>;
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};
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pinctrl_lpi2c1: lpi2c1grp {
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fsl,pins = <
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SC_P_GPT0_CLK_DMA_I2C1_SCL 0xc600004c
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SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c
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>;
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};
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pinctrl_lpi2c2: lpi2c2grp {
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fsl,pins = <
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SC_P_GPT1_CLK_DMA_I2C2_SCL 0xc600004c
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SC_P_GPT1_CAPTURE_DMA_I2C2_SDA 0xc600004c
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>;
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};
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pinctrl_lpuart0: lpuart0grp {
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fsl,pins = <
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SC_P_UART0_RX_DMA_UART0_RX 0x06000020
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SC_P_UART0_TX_DMA_UART0_TX 0x06000020
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>;
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};
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pinctrl_rtc_mc_8803: rtc-mc-8803-grp{
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fsl,pins = <
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SC_P_SIM0_POWER_EN_DMA_I2C3_SDA 0xc600004c
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SC_P_SIM0_PD_DMA_I2C3_SCL 0xc600004c
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
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SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
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SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
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SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
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SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
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SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
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SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
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SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
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SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
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SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
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SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041
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SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
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>;
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};
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pinctrl_usdhc1_100mhz: usdhc1grp-100mhz {
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fsl,pins = <
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SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
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SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
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SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
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SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
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SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
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SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
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SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
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SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
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SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
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SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
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SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040
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SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
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>;
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};
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pinctrl_usdhc1_200mhz: usdhc1grp-200mhz {
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fsl,pins = <
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SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
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SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
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SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
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SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
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SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
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SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
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SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
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SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
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SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
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SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
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SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040
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SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
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>;
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};
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pinctrl_usdhc2_gpio: usdhc2grpgpio {
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fsl,pins = <
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SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000020
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SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO08 0x00000020
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>;
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};
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pinctrl_usdhc3_gpio: usdhc3grpgpio {
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fsl,pins = <
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SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021
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SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
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SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
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SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
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SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
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SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
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SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
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SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
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fsl,pins = <
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SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
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SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
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SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
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SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
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SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
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SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
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SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
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fsl,pins = <
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SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
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SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
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SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
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SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
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SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
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SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
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SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
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>;
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};
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pinctrl_usdhc3: usdhc3grp {
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fsl,pins = <
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SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041
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SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021
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SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021
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SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021
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SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021
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SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021
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SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021
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>;
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};
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pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
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fsl,pins = <
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SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040
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SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020
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SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020
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SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020
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SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020
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SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020
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SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020
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>;
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};
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pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
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fsl,pins = <
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SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040
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SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020
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SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020
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SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020
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SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020
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SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020
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SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020
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>;
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};
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};
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};
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&gpio2 {
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status = "okay";
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};
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&gpio4 {
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status = "okay";
|
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};
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&gpio5 {
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status = "okay";
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};
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&usdhc1 {
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bus-width = <8>;
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non-removable;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
|
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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status = "okay";
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||||
};
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&usdhc2 {
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bus-width = <4>;
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cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
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vmmc-supply = <®_usdhc2_vmmc>;
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status = "okay";
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};
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&usdhc3 {
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bus-width = <4>;
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cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
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no-1-8-v;
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pinctrl-names = "default","state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>;
|
||||
wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
fsl,ar8031-phy-fixup;
|
||||
fsl,magic-packet;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec1>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy0>;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy0: ethernet-phy@4 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fec2 {
|
||||
fsl,ar8031-phy-fixup;
|
||||
fsl,magic-packet;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec2>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy1>;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy1: ethernet-phy@4 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lpi2c1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lpi2c2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_rtc_mc_8803>;
|
||||
status = "okay";
|
||||
|
||||
rv8803@32 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "microcrystal,rv8803";
|
||||
reg = <0x32>;
|
||||
};
|
||||
|
||||
24c02@50 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "atmel,24c04";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
||||
&lpuart0 { /* console */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lpuart0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -41,6 +41,8 @@ enum mxc_clock {
|
|||
MXC_SATA_CLK,
|
||||
MXC_NFC_CLK,
|
||||
MXC_I2C_CLK,
|
||||
MXC_LCDIF1_CLK,
|
||||
MXC_LCDIF2_CLK,
|
||||
};
|
||||
|
||||
enum ldb_di_clock {
|
||||
|
|
|
|||
|
|
@ -91,6 +91,13 @@ config TARGET_IMX8QM_ROM7720_A1
|
|||
select SUPPORT_SPL
|
||||
select IMX8QM
|
||||
|
||||
config TARGET_IMX8QM_DMSSE20_A1
|
||||
bool "Support i.MX8QM DMS-SE20-A1 board"
|
||||
select BINMAN
|
||||
select BOARD_LATE_INIT
|
||||
select SUPPORT_SPL
|
||||
select IMX8QM
|
||||
|
||||
config TARGET_IMX8QXP_MEK
|
||||
bool "Support i.MX8QXP MEK board"
|
||||
select BINMAN
|
||||
|
|
@ -105,6 +112,7 @@ endchoice
|
|||
source "board/freescale/imx8qm_mek/Kconfig"
|
||||
source "board/freescale/imx8qxp_mek/Kconfig"
|
||||
source "board/congatec/cgtqmx8/Kconfig"
|
||||
source "board/advantech/imx8qm_dmsse20_a1/Kconfig"
|
||||
source "board/advantech/imx8qm_rom7720_a1/Kconfig"
|
||||
source "board/toradex/apalis-imx8/Kconfig"
|
||||
source "board/toradex/colibri-imx8x/Kconfig"
|
||||
|
|
|
|||
|
|
@ -60,6 +60,12 @@ config TARGET_IMX8MQ_PHANBELL
|
|||
select IMX8MQ
|
||||
select IMX8M_LPDDR4
|
||||
|
||||
config TARGET_IMX8MQ_REFORM2
|
||||
bool "imx8mq_reform2"
|
||||
select BINMAN
|
||||
select IMX8MQ
|
||||
select IMX8M_LPDDR4
|
||||
|
||||
config TARGET_IMX8MM_DATA_MODUL_EDM_SBC
|
||||
bool "Data Modul eDM SBC i.MX8M Mini"
|
||||
select BINMAN
|
||||
|
|
@ -362,6 +368,7 @@ source "board/kontron/pitx_imx8m/Kconfig"
|
|||
source "board/kontron/sl-mx8mm/Kconfig"
|
||||
source "board/menlo/mx8menlo/Kconfig"
|
||||
source "board/msc/sm2s_imx8mp/Kconfig"
|
||||
source "board/mntre/imx8mq_reform2/Kconfig"
|
||||
source "board/phytec/phycore_imx8mm/Kconfig"
|
||||
source "board/phytec/phycore_imx8mp/Kconfig"
|
||||
source "board/purism/librem5/Kconfig"
|
||||
|
|
|
|||
|
|
@ -914,6 +914,8 @@ static int low_drive_gpu_freq(void *blob)
|
|||
|
||||
if (cnt != 7)
|
||||
printf("Warning: %s, assigned-clock-rates count %d\n", nodes_path_8mn[0], cnt);
|
||||
if (cnt < 2)
|
||||
return -1;
|
||||
|
||||
assignedclks[cnt - 1] = 200000000;
|
||||
assignedclks[cnt - 2] = 200000000;
|
||||
|
|
@ -1395,40 +1397,6 @@ usb_modify_speed:
|
|||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_OF_BOARD_FIXUP
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
int board_fix_fdt(void *fdt)
|
||||
{
|
||||
if (is_imx8mpul()) {
|
||||
int i = 0;
|
||||
int nodeoff, ret;
|
||||
const char *status = "disabled";
|
||||
static const char * const dsi_nodes[] = {
|
||||
"/soc@0/bus@32c00000/mipi_dsi@32e60000",
|
||||
"/soc@0/bus@32c00000/lcd-controller@32e80000",
|
||||
"/dsi-host"
|
||||
};
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(dsi_nodes); i++) {
|
||||
nodeoff = fdt_path_offset(fdt, dsi_nodes[i]);
|
||||
if (nodeoff > 0) {
|
||||
set_status:
|
||||
ret = fdt_setprop(fdt, nodeoff, "status", status,
|
||||
strlen(status) + 1);
|
||||
if (ret == -FDT_ERR_NOSPACE) {
|
||||
ret = fdt_increase_size(fdt, 512);
|
||||
if (!ret)
|
||||
goto set_status;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if !CONFIG_IS_ENABLED(SYSRESET)
|
||||
void reset_cpu(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -213,6 +213,7 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num)
|
|||
static u32 decode_pll(enum pll_clocks pll, u32 infreq)
|
||||
{
|
||||
u32 div, test_div, pll_num, pll_denom;
|
||||
u64 temp64;
|
||||
|
||||
switch (pll) {
|
||||
case PLL_SYS:
|
||||
|
|
@ -272,7 +273,10 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq)
|
|||
}
|
||||
test_div = 1 << (2 - test_div);
|
||||
|
||||
return infreq * (div + pll_num / pll_denom) / test_div;
|
||||
temp64 = (u64)infreq;
|
||||
temp64 *= pll_num;
|
||||
do_div(temp64, pll_denom);
|
||||
return infreq * div + (unsigned long)temp64;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -414,6 +418,60 @@ static u32 get_uart_clk(void)
|
|||
return freq / (uart_podf + 1);
|
||||
}
|
||||
|
||||
static u32 get_lcd_clk(unsigned int ifnum)
|
||||
{
|
||||
u32 pll_rate;
|
||||
u32 pred, postd;
|
||||
|
||||
if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl() &&
|
||||
!is_mx6sll()) {
|
||||
debug("This chip does't support lcd\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
pll_rate = decode_pll(PLL_VIDEO, MXC_HCLK);
|
||||
if (ifnum == 1) {
|
||||
if (!is_mx6sl()) {
|
||||
pred = __raw_readl(&imx_ccm->cscdr2);
|
||||
pred &= MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK;
|
||||
pred = pred >> MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET;
|
||||
|
||||
postd = readl(&imx_ccm->cbcmr);
|
||||
postd &= MXC_CCM_CBCMR_LCDIF1_PODF_MASK;
|
||||
postd = postd >> MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET;
|
||||
} else {
|
||||
pred = __raw_readl(&imx_ccm->cscdr2);
|
||||
pred &= MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK;
|
||||
pred = pred >> MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET;
|
||||
|
||||
postd = readl(&imx_ccm->cscmr1);
|
||||
postd &= MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET;
|
||||
postd = postd >> MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET;
|
||||
}
|
||||
} else if (ifnum == 2) {
|
||||
if (is_mx6sx()) {
|
||||
pred = __raw_readl(&imx_ccm->cscdr2);
|
||||
pred &= MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK;
|
||||
pred = pred >> MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET;
|
||||
|
||||
postd = readl(&imx_ccm->cscmr1);
|
||||
postd &= MXC_CCM_CSCMR1_LCDIF2_PODF_MASK;
|
||||
postd = postd >> MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET;
|
||||
|
||||
} else {
|
||||
goto if_err;
|
||||
}
|
||||
} else {
|
||||
goto if_err;
|
||||
}
|
||||
|
||||
return DIV_ROUND_UP_ULL((u64)pll_rate, (postd + 1) * (pred + 1));
|
||||
|
||||
if_err:
|
||||
debug("This chip not support lcd iterface %d\n", ifnum);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u32 get_cspi_clk(void)
|
||||
{
|
||||
u32 reg, cspi_podf;
|
||||
|
|
@ -744,6 +802,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
|
|||
}
|
||||
|
||||
enable_lcdif_clock(base_addr, 1);
|
||||
debug("pixel clock = %u\n", mxc_get_clock(MXC_LCDIF1_CLK));
|
||||
} else if (is_mx6sx()) {
|
||||
/* Setting LCDIF2 for i.MX6SX */
|
||||
if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
|
||||
|
|
@ -765,6 +824,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
|
|||
MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
|
||||
|
||||
enable_lcdif_clock(base_addr, 1);
|
||||
debug("pixel clock = %u\n", mxc_get_clock(MXC_LCDIF2_CLK));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1269,6 +1329,10 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
|
|||
return get_usdhc_clk(3);
|
||||
case MXC_SATA_CLK:
|
||||
return get_ahb_clk();
|
||||
case MXC_LCDIF1_CLK:
|
||||
return get_lcd_clk(1);
|
||||
case MXC_LCDIF2_CLK:
|
||||
return get_lcd_clk(2);
|
||||
default:
|
||||
printf("Unsupported MXC CLK: %d\n", clk);
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -70,6 +70,8 @@ enum boot_device get_boot_device(void)
|
|||
boot_dev = SPI_NOR_BOOT;
|
||||
break;
|
||||
case BT_DEV_TYPE_USB:
|
||||
if (!is_imx8ulp() && !is_imx9())
|
||||
boot_instance = 0;
|
||||
boot_dev = boot_instance + USB_BOOT;
|
||||
break;
|
||||
default:
|
||||
|
|
|
|||
15
board/advantech/imx8qm_dmsse20_a1/Kconfig
Normal file
15
board/advantech/imx8qm_dmsse20_a1/Kconfig
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
if TARGET_IMX8QM_DMSSE20_A1
|
||||
|
||||
config SYS_BOARD
|
||||
default "imx8qm_dmsse20_a1"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "advantech"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "imx8qm_dmsse20"
|
||||
|
||||
config IMX_CONFIG
|
||||
default "board/advantech/imx8qm_dmsse20_a1/imximage.cfg"
|
||||
|
||||
endif
|
||||
7
board/advantech/imx8qm_dmsse20_a1/MAINTAINERS
Normal file
7
board/advantech/imx8qm_dmsse20_a1/MAINTAINERS
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
i.MX8QM ROM DMSSE20 a1 BOARD
|
||||
M: Oliver Graute <oliver.graute@kococonnector.com>
|
||||
S: Maintained
|
||||
F: board/advantech/imx8qm_dmsse20_a1/
|
||||
F: arch/arm/dts/imx8qm-dmsse20-a1.dtb
|
||||
F: include/configs/imx8qm_dmsse20.h
|
||||
F: configs/imx8qm_dmsse20a1_defconfig
|
||||
8
board/advantech/imx8qm_dmsse20_a1/Makefile
Normal file
8
board/advantech/imx8qm_dmsse20_a1/Makefile
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
#
|
||||
# Copyright 2017 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += imx8qm_dmsse20_a1.o
|
||||
obj-$(CONFIG_SPL_BUILD) += spl.o
|
||||
48
board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env
Normal file
48
board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
script=boot.scr
|
||||
image=Image
|
||||
panel=NULL
|
||||
console=ttyLP0
|
||||
earlycon=lpuart32,0x5a060000
|
||||
fdt_addr=0x83000000
|
||||
boot_fdt=try
|
||||
fdt_file=imx8qm-dmsse20-a1.dtb
|
||||
mmcdev= __stringify(CONFIG_SYS_MMC_ENV_DEV)
|
||||
mmcpart= __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART)
|
||||
mmcroot=/dev/mmcblk1p2 rootwait rw
|
||||
mmcautodetect=yes
|
||||
mmcargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} root=${mmcroot}
|
||||
loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};
|
||||
bootscript=echo Running bootscript from mmc ...; source
|
||||
loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
|
||||
loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}
|
||||
mmcboot=echo Booting from mmc ...;
|
||||
run mmcargs;
|
||||
if test ${boot_fdt} = yes || test ${boot_fdt} = try; then
|
||||
if run loadfdt; then
|
||||
booti ${loadaddr} - ${fdt_addr};
|
||||
else
|
||||
echo WARN: Cannot load the DT;
|
||||
fi;
|
||||
else
|
||||
echo wait for boot;
|
||||
fi;
|
||||
netargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate}
|
||||
root=/dev/nfs
|
||||
ip=dhcp mac=${ethaddr} nfsroot=${serverip}:${nfsroot},v3,tcp rw
|
||||
netboot=echo Booting from net ...;
|
||||
run netargs;
|
||||
if test ${ip_dyn} = yes; then
|
||||
setenv get_cmd dhcp;
|
||||
else
|
||||
setenv get_cmd tftp;
|
||||
fi;
|
||||
${get_cmd} ${loadaddr} ${image};
|
||||
if test ${boot_fdt} = yes || test ${boot_fdt} = try; then
|
||||
if ${get_cmd} ${fdt_addr} ${fdt_file}; then
|
||||
booti ${loadaddr} - ${fdt_addr};
|
||||
else
|
||||
echo WARN: Cannot load the DT;
|
||||
fi;
|
||||
else
|
||||
booti;
|
||||
fi;
|
||||
188
board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c
Normal file
188
board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c
Normal file
|
|
@ -0,0 +1,188 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2017-2018 NXP
|
||||
* Copyright 2019-2023 Kococonnector GmbH
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <errno.h>
|
||||
#include <linux/libfdt.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/sci/sci.h>
|
||||
#include <asm/arch/imx8-pins.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
/* #include <power-domain.h> */
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
|
||||
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||
|
||||
static iomux_cfg_t uart0_pads[] = {
|
||||
SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
sc_pm_clock_rate_t rate = SC_80MHZ;
|
||||
int ret;
|
||||
|
||||
/* Set UART0 clock root to 80 MHz */
|
||||
ret = sc_pm_setup_uart(SC_R_UART_0, rate);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
setup_iomux_uart();
|
||||
|
||||
/* This is needed to because Kernel do not Power Up DC_0 */
|
||||
sc_pm_set_resource_power_mode(-1, SC_R_DC_0, SC_PM_PW_MODE_ON);
|
||||
sc_pm_set_resource_power_mode(-1, SC_R_GPIO_5, SC_PM_PW_MODE_ON);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if IS_ENABLED(CONFIG_FEC_MXC)
|
||||
#include <miiphy.h>
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
|
||||
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
|
||||
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MXC_GPIO
|
||||
|
||||
#define LVDS_ENABLE IMX_GPIO_NR(1, 6)
|
||||
#define MIPI_ENABLE IMX_GPIO_NR(1, 7)
|
||||
|
||||
#define BB_GPIO_3V3_1 IMX_GPIO_NR(4, 20)
|
||||
#define BB_GPIO_3V3_2 IMX_GPIO_NR(4, 24)
|
||||
#define BB_GPIO_3V3_3 IMX_GPIO_NR(4, 23)
|
||||
|
||||
static void board_gpio_init(void)
|
||||
{
|
||||
/* Enable BB 3V3 */
|
||||
gpio_request(BB_GPIO_3V3_1, "bb_3v3_1");
|
||||
gpio_direction_output(BB_GPIO_3V3_1, 1);
|
||||
gpio_request(BB_GPIO_3V3_2, "bb_3v3_2");
|
||||
gpio_direction_output(BB_GPIO_3V3_2, 1);
|
||||
gpio_request(BB_GPIO_3V3_3, "bb_3v3_3");
|
||||
gpio_direction_output(BB_GPIO_3V3_3, 1);
|
||||
|
||||
/* enable LVDS SAS boards */
|
||||
gpio_request(LVDS_ENABLE, "lvds_enable");
|
||||
gpio_direction_output(LVDS_ENABLE, 1);
|
||||
|
||||
/* enable MIPI SAS boards */
|
||||
gpio_request(MIPI_ENABLE, "mipi_enable");
|
||||
gpio_direction_output(MIPI_ENABLE, 1);
|
||||
}
|
||||
#endif
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: DMS-SE20A1 8GB\n");
|
||||
build_info();
|
||||
print_bootinfo();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_XEN))
|
||||
return 0;
|
||||
|
||||
#ifdef CONFIG_MXC_GPIO
|
||||
board_gpio_init();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void board_quiesce_devices(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_XEN)) {
|
||||
/* Clear magic number to let xen know uboot is over */
|
||||
writel(0x0, (void __iomem *)0x80000000);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
void detail_board_ddr_info(void)
|
||||
{
|
||||
puts("\nDDR ");
|
||||
}
|
||||
|
||||
/*
|
||||
* Board specific reset that is system reset.
|
||||
*/
|
||||
void reset_cpu(void)
|
||||
{
|
||||
puts("SCI reboot request");
|
||||
|
||||
while (1)
|
||||
putc('.');
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF_BOARD_SETUP
|
||||
int ft_board_setup(void *blob, struct bd_info *bd)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_mmc_get_env_dev(int devno)
|
||||
{
|
||||
/* Use EMMC */
|
||||
if (IS_ENABLED(CONFIG_XEN))
|
||||
return 0;
|
||||
|
||||
return devno;
|
||||
}
|
||||
|
||||
int mmc_map_to_kernel_blk(int dev_no)
|
||||
{
|
||||
/* Use EMMC */
|
||||
if (IS_ENABLED(CONFIG_XEN))
|
||||
return 0;
|
||||
|
||||
return dev_no;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||
env_set("board_name", "DMS-SE20A1");
|
||||
env_set("board_rev", "iMX8QM");
|
||||
#endif
|
||||
|
||||
env_set("sec_boot", "no");
|
||||
#ifdef CONFIG_AHAB_BOOT
|
||||
env_set("sec_boot", "yes");
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
23
board/advantech/imx8qm_dmsse20_a1/imximage.cfg
Normal file
23
board/advantech/imx8qm_dmsse20_a1/imximage.cfg
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* Copyright 2017-2018 NXP
|
||||
* Copyright 2019-2023 Kococonnector GmbH
|
||||
*/
|
||||
|
||||
#define __ASSEMBLY__
|
||||
|
||||
/* Boot from SD, sector size 0x400 */
|
||||
/* SoC type IMX8QM */
|
||||
BOOT_FROM sd
|
||||
|
||||
SOC_TYPE IMX8QM
|
||||
/* Append seco container image */
|
||||
APPEND mx8qm-ahab-container.img
|
||||
/* Create the 2nd container */
|
||||
CONTAINER
|
||||
/* Add scfw image with exec attribute */
|
||||
IMAGE SCU mx8qm-val-scfw-tcm.bin
|
||||
/* Add ATF image with exec attribute */
|
||||
IMAGE A35 bl31.bin 0x80000000
|
||||
/* Add U-Boot image with load attribute */
|
||||
DATA A35 u-boot-dtb.bin 0x80020000
|
||||
223
board/advantech/imx8qm_dmsse20_a1/spl.c
Normal file
223
board/advantech/imx8qm_dmsse20_a1/spl.c
Normal file
|
|
@ -0,0 +1,223 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright 2017-2018 NXP
|
||||
* Copyright 2019-2023 Kococonnector GmbH
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <spl.h>
|
||||
#include <init.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/sci/sci.h>
|
||||
#include <asm/arch/imx8-pins.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <fsl_esdhc_imx.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
|
||||
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||
|
||||
#define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
|
||||
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||
|
||||
#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | \
|
||||
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||
|
||||
#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
|
||||
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||
|
||||
#define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
|
||||
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||
|
||||
#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
|
||||
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||
|
||||
#define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
|
||||
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||
|
||||
#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
|
||||
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||
#ifdef CONFIG_FSL_ESDHC_IMX
|
||||
|
||||
#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22)
|
||||
#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12)
|
||||
|
||||
static struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = {
|
||||
{USDHC1_BASE_ADDR, 0, 8},
|
||||
{USDHC3_BASE_ADDR, 0, 4},
|
||||
};
|
||||
|
||||
static iomux_cfg_t emmc0[] = {
|
||||
SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
|
||||
SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_cfg_t usdhc2_sd[] = {
|
||||
SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
|
||||
SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_USDHC2_WP | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
|
||||
};
|
||||
|
||||
void init_clk_usdhc(u32 index);
|
||||
|
||||
int board_mmc_init(struct bd_info *bis)
|
||||
{
|
||||
int i, ret;
|
||||
|
||||
/*
|
||||
* According to the board_mmc_init() the following map is done:
|
||||
* (U-Boot device node) (Physical Port)
|
||||
* mmc0 USDHC1
|
||||
* mmc1 USDHC2
|
||||
* mmc2 USDHC3
|
||||
*/
|
||||
for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
|
||||
switch (i) {
|
||||
case 0:
|
||||
ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON);
|
||||
if (ret != SC_ERR_NONE)
|
||||
return ret;
|
||||
|
||||
imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0));
|
||||
init_clk_usdhc(0);
|
||||
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
break;
|
||||
case 1:
|
||||
ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, SC_PM_PW_MODE_ON);
|
||||
if (ret != SC_ERR_NONE)
|
||||
return ret;
|
||||
ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, SC_PM_PW_MODE_ON);
|
||||
if (ret != SC_ERR_NONE)
|
||||
return ret;
|
||||
|
||||
imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd));
|
||||
init_clk_usdhc(2);
|
||||
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
gpio_request(USDHC2_CD_GPIO, "sd2_cd");
|
||||
gpio_direction_input(USDHC2_CD_GPIO);
|
||||
break;
|
||||
default:
|
||||
printf("Warning: you configured more USDHC controllers"
|
||||
"(%d) than supported by the board\n", i + 1);
|
||||
return 0;
|
||||
}
|
||||
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
|
||||
if (ret) {
|
||||
printf("Warning: failed to initialize mmc dev %d\n", i);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
int ret = 0;
|
||||
|
||||
switch (cfg->esdhc_base) {
|
||||
case USDHC1_BASE_ADDR:
|
||||
ret = 1;
|
||||
break;
|
||||
case USDHC2_BASE_ADDR:
|
||||
ret = !gpio_get_value(USDHC1_CD_GPIO);
|
||||
break;
|
||||
case USDHC3_BASE_ADDR:
|
||||
ret = !gpio_get_value(USDHC2_CD_GPIO);
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_FSL_ESDHC_IMX */
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
#if defined(CONFIG_SPL_SPI_SUPPORT)
|
||||
if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
|
||||
if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_ON)) {
|
||||
puts("Warning: failed to initialize FSPI0\n");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
puts("Normal Boot\n");
|
||||
}
|
||||
|
||||
void spl_board_prepare_for_boot(void)
|
||||
{
|
||||
#if defined(CONFIG_SPL_SPI_SUPPORT)
|
||||
if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
|
||||
if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_OFF)) {
|
||||
puts("Warning: failed to turn off FSPI0\n");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_LOAD_FIT
|
||||
int board_fit_config_name_match(const char *name)
|
||||
{
|
||||
/* Just empty function now - can't decide what to choose */
|
||||
debug("%s: %s\n", __func__, name);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
/* Clear global data */
|
||||
memset((void *)gd, 0, sizeof(gd_t));
|
||||
|
||||
arch_cpu_init();
|
||||
|
||||
board_early_init_f();
|
||||
|
||||
timer_init();
|
||||
|
||||
preloader_console_init();
|
||||
|
||||
/* Clear the BSS. */
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
15
board/mntre/imx8mq_reform2/Kconfig
Normal file
15
board/mntre/imx8mq_reform2/Kconfig
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
if TARGET_IMX8MQ_REFORM2
|
||||
|
||||
config SYS_BOARD
|
||||
default "imx8mq_reform2"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "mntre"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "imx8mq_reform2"
|
||||
|
||||
config IMX_CONFIG
|
||||
default "arch/arm/mach-imx/imx8m/imximage.cfg"
|
||||
|
||||
endif
|
||||
7
board/mntre/imx8mq_reform2/MAINTAINERS
Normal file
7
board/mntre/imx8mq_reform2/MAINTAINERS
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
REFORM2 IMX8MQ BOARD
|
||||
M: Lukas F. Hartmann <lukas@mntre.com>
|
||||
M: Patrick Wildt <patrick@blueri.se>
|
||||
S: Maintained
|
||||
F: board/mntre/imx8mq_reform2/
|
||||
F: include/configs/imx8mq_reform2.h
|
||||
F: configs/imx8mq_reform2_defconfig
|
||||
12
board/mntre/imx8mq_reform2/Makefile
Normal file
12
board/mntre/imx8mq_reform2/Makefile
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
#
|
||||
# Copyright 2017 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += imx8mq_reform2.o
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
obj-y += spl.o
|
||||
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
|
||||
endif
|
||||
171
board/mntre/imx8mq_reform2/imx8mq_reform2.c
Normal file
171
board/mntre/imx8mq_reform2/imx8mq_reform2.c
Normal file
|
|
@ -0,0 +1,171 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
* Copyright (C) 2018, Boundary Devices <info@boundarydevices.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <env.h>
|
||||
#include <init.h>
|
||||
#include <malloc.h>
|
||||
#include <errno.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/io.h>
|
||||
#include <miiphy.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/mach-imx/iomux-v3.h>
|
||||
#include <asm-generic/gpio.h>
|
||||
#include <fsl_esdhc_imx.h>
|
||||
#include <mmc.h>
|
||||
#include <asm/arch/imx8mq_pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/mach-imx/gpio.h>
|
||||
#include <asm/mach-imx/mxc_i2c.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <spl.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/delay.h>
|
||||
#include <power/pmic.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
||||
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
|
||||
|
||||
static iomux_v3_cfg_t const wdog_pads[] = {
|
||||
IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
|
||||
};
|
||||
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
|
||||
set_wdog_reset(wdog);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
|
||||
#define PHY_RESET IMX_GPIO_NR(1, 9)
|
||||
#define PHY_RX_CTL IMX_GPIO_NR(1, 24)
|
||||
#define PHY_RXC IMX_GPIO_NR(1, 25)
|
||||
#define PHY_RD0 IMX_GPIO_NR(1, 26)
|
||||
#define PHY_RD1 IMX_GPIO_NR(1, 27)
|
||||
#define PHY_RD2 IMX_GPIO_NR(1, 28)
|
||||
#define PHY_RD3 IMX_GPIO_NR(1, 29)
|
||||
|
||||
#define STRAP_AR8035 (0x28) // 0010 1000
|
||||
|
||||
static const iomux_v3_cfg_t enet_ar8035_gpio_pads[] = {
|
||||
IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(PAD_CTL_DSE6),
|
||||
IMX8MQ_PAD_ENET_RD0__GPIO1_IO26 | MUX_PAD_CTRL(0x91),
|
||||
IMX8MQ_PAD_ENET_RD1__GPIO1_IO27 | MUX_PAD_CTRL(0x91),
|
||||
IMX8MQ_PAD_ENET_RD2__GPIO1_IO28 | MUX_PAD_CTRL(0x91),
|
||||
IMX8MQ_PAD_ENET_RD3__GPIO1_IO29 | MUX_PAD_CTRL(0xd1),
|
||||
IMX8MQ_PAD_ENET_RX_CTL__GPIO1_IO24 | MUX_PAD_CTRL(0x91),
|
||||
/* 1.8V(1)/1.5V select(0) */
|
||||
IMX8MQ_PAD_ENET_RXC__GPIO1_IO25 | MUX_PAD_CTRL(0xd1),
|
||||
};
|
||||
|
||||
static const iomux_v3_cfg_t enet_ar8035_pads[] = {
|
||||
IMX8MQ_PAD_ENET_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(0x91),
|
||||
IMX8MQ_PAD_ENET_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(0x91),
|
||||
IMX8MQ_PAD_ENET_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(0x91),
|
||||
IMX8MQ_PAD_ENET_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(0x91),
|
||||
IMX8MQ_PAD_ENET_RX_CTL__ENET_RGMII_RX_CTL | MUX_PAD_CTRL(0x91),
|
||||
IMX8MQ_PAD_ENET_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(0x91),
|
||||
};
|
||||
|
||||
static void setup_fec(void)
|
||||
{
|
||||
struct iomuxc_gpr_base_regs *gpr =
|
||||
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
|
||||
|
||||
/* Pull PHY into reset */
|
||||
gpio_request(PHY_RESET, "fec_rst");
|
||||
gpio_direction_output(PHY_RESET, 0);
|
||||
|
||||
/* Configure ethernet pins value as GPIOs */
|
||||
gpio_request(PHY_RD0, "fec_rd0");
|
||||
gpio_direction_output(PHY_RD0, 0);
|
||||
gpio_request(PHY_RD1, "fec_rd1");
|
||||
gpio_direction_output(PHY_RD1, 0);
|
||||
gpio_request(PHY_RD2, "fec_rd2");
|
||||
gpio_direction_output(PHY_RD2, 0);
|
||||
gpio_request(PHY_RD3, "fec_rd3");
|
||||
gpio_direction_output(PHY_RD3, 1);
|
||||
gpio_request(PHY_RX_CTL, "fec_rx_ctl");
|
||||
gpio_direction_output(PHY_RX_CTL, 0);
|
||||
gpio_request(PHY_RXC, "fec_rxc");
|
||||
gpio_direction_output(PHY_RXC, 1);
|
||||
|
||||
/* Set ethernet pins to GPIO to bootstrap PHY */
|
||||
imx_iomux_v3_setup_multiple_pads(enet_ar8035_gpio_pads,
|
||||
ARRAY_SIZE(enet_ar8035_gpio_pads));
|
||||
|
||||
/* Use 125M anatop REF_CLK1 for ENET1, not from external */
|
||||
clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
|
||||
/* Enable RGMII TX clk output */
|
||||
setbits_le32(&gpr->gpr[1], BIT(22));
|
||||
set_clk_enet(ENET_125MHZ);
|
||||
|
||||
/* 1 ms minimum reset pulse for ar8035 */
|
||||
mdelay(1);
|
||||
|
||||
/* Release PHY from reset */
|
||||
gpio_set_value(PHY_RESET, 1);
|
||||
|
||||
/* strap hold time for AR8035, 5 fails, 6 works, so 12 should be safe */
|
||||
udelay(12);
|
||||
|
||||
/* Change ethernet pins back to normal function */
|
||||
imx_iomux_v3_setup_multiple_pads(enet_ar8035_pads,
|
||||
ARRAY_SIZE(enet_ar8035_pads));
|
||||
}
|
||||
#endif
|
||||
|
||||
#define USB1_HUB_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
|
||||
#define USB1_HUB_RESET IMX_GPIO_NR(1, 14)
|
||||
|
||||
static void setup_usb(void)
|
||||
{
|
||||
imx_iomux_v3_setup_pad(IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 |
|
||||
MUX_PAD_CTRL(USB1_HUB_PAD_CTRL));
|
||||
gpio_request(USB1_HUB_RESET, "usb1_rst");
|
||||
gpio_direction_output(USB1_HUB_RESET, 0);
|
||||
mdelay(10);
|
||||
gpio_set_value(USB1_HUB_RESET, 1);
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
setup_fec();
|
||||
#endif
|
||||
|
||||
setup_usb();
|
||||
|
||||
#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_DWC3)
|
||||
init_usb_clk();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_mmc_get_env_dev(int devno)
|
||||
{
|
||||
return devno;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||
env_set("board_name", "Reform2");
|
||||
env_set("board_rev", "iMX8MQ");
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
1014
board/mntre/imx8mq_reform2/lpddr4_timing.c
Normal file
1014
board/mntre/imx8mq_reform2/lpddr4_timing.c
Normal file
File diff suppressed because it is too large
Load diff
95
board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
Normal file
95
board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
Normal file
|
|
@ -0,0 +1,95 @@
|
|||
/*
|
||||
* Copyright Boundary Devices
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#include <config.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <asm/arch/ddr.h>
|
||||
#include <asm/arch/lpddr4_define.h>
|
||||
|
||||
/* MNT Reform2 */
|
||||
#define CFG_DDR_MB 4096
|
||||
#define CFG_DDR_RANK_BITS 1
|
||||
#define CFG_DDR_CHANNEL_CNT 2
|
||||
|
||||
#ifdef WR_POST_EXT_3200
|
||||
#define CH2_VAL_INIT4 ((LPDDR4_MR3 << 16) | 0x00020008)
|
||||
#else
|
||||
#define CH2_VAL_INIT4 ((LPDDR4_MR3 << 16) | 8)
|
||||
#endif
|
||||
|
||||
#if CFG_DDR_MB == 1024
|
||||
/* Address map is from MSB 28: r14, r13-r0, b2-b0, c9-c0 */
|
||||
#define CH2_VAL_DDRC_ADDRMAP0_R0 0x0000001F
|
||||
#define CH2_VAL_DDRC_ADDRMAP6_R0 0x0F070707
|
||||
|
||||
#elif CFG_DDR_MB == 2048
|
||||
/* Address map is from MSB 28: r15, r14, r13-r0, b2-b0, c9-c0 */
|
||||
#define CH2_VAL_DDRC_ADDRMAP0_R0 0x0000001F
|
||||
#define CH2_VAL_DDRC_ADDRMAP6_R0 0x07070707
|
||||
/* Address map is from MSB 28: cs, r14, r13-r0, b2-b0, c9-c0 */
|
||||
#define CH2_VAL_DDRC_ADDRMAP0_R1 0x00000016
|
||||
#define CH2_VAL_DDRC_ADDRMAP6_R1 0x0F070707
|
||||
|
||||
#elif CFG_DDR_MB == 3072
|
||||
/* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
|
||||
#define CH2_VAL_DDRC_ADDRMAP0_R1 0x00000015
|
||||
#define CH2_VAL_DDRC_ADDRMAP6_R1 0x48080707
|
||||
|
||||
#elif CFG_DDR_MB == 4096
|
||||
/* Address map is from MSB 29: cs, r15, r14, r13-r0, b2-b0, c9-c0 */
|
||||
#define CH2_VAL_DDRC_ADDRMAP0_R1 0x00000017
|
||||
#define CH2_VAL_DDRC_ADDRMAP6_R1 0x07070707
|
||||
#else
|
||||
#error unsupported memory size
|
||||
#endif
|
||||
|
||||
#define LPDDR4_CS_R0 0x1 /* 0 rank bits, 1 chip select */
|
||||
#define LPDDR4_CS_R1 0x3 /* 1 rank bit, 2 chip selects */
|
||||
|
||||
#if (CFG_DDR_RANK_BITS == 0) || !defined(CH2_VAL_DDRC_ADDRMAP0_R1)
|
||||
#ifdef CH2_VAL_DDRC_ADDRMAP0_R0
|
||||
#define CH2_LPDDR4_CS LPDDR4_CS_R0
|
||||
#define CH2_VAL_DDRC_ADDRMAP0 CH2_VAL_DDRC_ADDRMAP0_R0
|
||||
#define CH2_VAL_DDRC_ADDRMAP6 CH2_VAL_DDRC_ADDRMAP6_R0
|
||||
#else
|
||||
#error unsupported memory rank/size
|
||||
#endif
|
||||
/*
|
||||
* rank0 will succeed, even if really rank 1, so we need
|
||||
* to probe memory if rank0 succeeds
|
||||
*/
|
||||
#if defined(CH2_VAL_DDRC_ADDRMAP0_R0) && defined(CH2_VAL_DDRC_ADDRMAP0_R1)
|
||||
#define CH2_LPDDR4_CS_NEW LPDDR4_CS_R1
|
||||
#define CH2_VAL_DDRC_ADDRMAP0_NEW CH2_VAL_DDRC_ADDRMAP0_R1
|
||||
#define CH2_VAL_DDRC_ADDRMAP6_NEW CH2_VAL_DDRC_ADDRMAP6_R1
|
||||
#endif
|
||||
|
||||
#elif (CFG_DDR_RANK_BITS == 1) || !defined(CH2_VAL_DDRC_ADDRMAP0_R0)
|
||||
#ifdef CH2_VAL_DDRC_ADDRMAP0_R1
|
||||
#define CH2_LPDDR4_CS LPDDR4_CS_R1
|
||||
#define CH2_VAL_DDRC_ADDRMAP0 CH2_VAL_DDRC_ADDRMAP0_R1
|
||||
#define CH2_VAL_DDRC_ADDRMAP6 CH2_VAL_DDRC_ADDRMAP6_R1
|
||||
#else
|
||||
#error unsupported memory rank/size
|
||||
#endif
|
||||
|
||||
#if defined(CH2_VAL_DDRC_ADDRMAP0_R0) && defined(CH2_VAL_DDRC_ADDRMAP0_R1)
|
||||
#define CH2_LPDDR4_CS_NEW LPDDR4_CS_R0
|
||||
#define CH2_VAL_DDRC_ADDRMAP0_NEW CH2_VAL_DDRC_ADDRMAP0_R0
|
||||
#define CH2_VAL_DDRC_ADDRMAP6_NEW CH2_VAL_DDRC_ADDRMAP6_R0
|
||||
#endif
|
||||
|
||||
#else
|
||||
#error unsupported rank bits
|
||||
#endif
|
||||
|
||||
#if (CFG_DDR_CHANNEL_CNT == 2)
|
||||
#if (CFG_DDR_RANK_BITS == 0) && !defined(CH2_VAL_DDRC_ADDRMAP0_R0)
|
||||
#error unsupported options
|
||||
#endif
|
||||
#if (CFG_DDR_RANK_BITS == 1) && !defined(CH2_VAL_DDRC_ADDRMAP0_R1)
|
||||
#error unsupported options
|
||||
#endif
|
||||
#endif
|
||||
260
board/mntre/imx8mq_reform2/spl.c
Normal file
260
board/mntre/imx8mq_reform2/spl.c
Normal file
|
|
@ -0,0 +1,260 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <hang.h>
|
||||
#include <image.h>
|
||||
#include <init.h>
|
||||
#include <log.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/io.h>
|
||||
#include <errno.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/ddr.h>
|
||||
#include <asm/arch/imx8mq_pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/mach-imx/iomux-v3.h>
|
||||
#include <asm/mach-imx/gpio.h>
|
||||
#include <asm/mach-imx/mxc_i2c.h>
|
||||
#include <fsl_esdhc_imx.h>
|
||||
#include <mmc.h>
|
||||
#include <linux/delay.h>
|
||||
#include <power/pmic.h>
|
||||
#include <spl.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
extern struct dram_timing_info dram_timing_ch2;
|
||||
|
||||
static void spl_dram_init(void)
|
||||
{
|
||||
ddr_init(&dram_timing_ch2);
|
||||
}
|
||||
|
||||
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
|
||||
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
|
||||
static struct i2c_pads_info i2c_pad_info1 = {
|
||||
.scl = {
|
||||
.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
|
||||
.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
|
||||
.gp = IMX_GPIO_NR(5, 14),
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
|
||||
.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
|
||||
.gp = IMX_GPIO_NR(5, 15),
|
||||
},
|
||||
};
|
||||
|
||||
#define USDHC2_VSEL IMX_GPIO_NR(1, 8)
|
||||
#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
|
||||
#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
int ret = 0;
|
||||
|
||||
switch (cfg->esdhc_base) {
|
||||
case USDHC1_BASE_ADDR:
|
||||
ret = 1;
|
||||
break;
|
||||
case USDHC2_BASE_ADDR:
|
||||
ret = !gpio_get_value(USDHC2_CD_GPIO);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
|
||||
PAD_CTL_FSEL2)
|
||||
#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
|
||||
|
||||
static iomux_v3_cfg_t const usdhc1_pads[] = {
|
||||
IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const usdhc2_pads[] = {
|
||||
IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
|
||||
IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
|
||||
IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
|
||||
IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
|
||||
IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
|
||||
IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
|
||||
IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
|
||||
IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(0x91),
|
||||
};
|
||||
|
||||
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
|
||||
{USDHC1_BASE_ADDR, 0, 8},
|
||||
{USDHC2_BASE_ADDR, 0, 4},
|
||||
};
|
||||
|
||||
int board_mmc_init(struct bd_info *bis)
|
||||
{
|
||||
int i, ret;
|
||||
/*
|
||||
* According to the board_mmc_init() the following map is done:
|
||||
* (U-Boot device node) (Physical Port)
|
||||
* mmc0 USDHC1
|
||||
* mmc1 USDHC2
|
||||
*/
|
||||
for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
|
||||
switch (i) {
|
||||
case 0:
|
||||
init_clk_usdhc(0);
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
|
||||
imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
|
||||
ARRAY_SIZE(usdhc1_pads));
|
||||
gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
|
||||
gpio_direction_output(USDHC1_PWR_GPIO, 0);
|
||||
udelay(500);
|
||||
gpio_direction_output(USDHC1_PWR_GPIO, 1);
|
||||
break;
|
||||
case 1:
|
||||
init_clk_usdhc(1);
|
||||
usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
|
||||
imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
|
||||
ARRAY_SIZE(usdhc2_pads));
|
||||
gpio_request(USDHC2_VSEL, "usdhc2_vsel");
|
||||
gpio_direction_output(USDHC2_VSEL, 0);
|
||||
break;
|
||||
default:
|
||||
printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define I2C1_PCA9546_RESET IMX_GPIO_NR(1, 4)
|
||||
#define ARM_DRAM_VSEL IMX_GPIO_NR(3, 24)
|
||||
#define DRAM_1P1_VSEL IMX_GPIO_NR(2, 11)
|
||||
#define SOC_GPU_VPU_VSEL IMX_GPIO_NR(2, 20)
|
||||
|
||||
#define I2C_MUX_ADDR 0x70
|
||||
#define I2C_FAN53555_ADDR 0x60
|
||||
|
||||
static iomux_v3_cfg_t const power_pads[] = {
|
||||
IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(0x46),
|
||||
};
|
||||
|
||||
int power_init_board(void)
|
||||
{
|
||||
uint8_t val;
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(power_pads,
|
||||
ARRAY_SIZE(usdhc2_pads));
|
||||
|
||||
/* Release I2C multiplexer reset */
|
||||
gpio_request(I2C1_PCA9546_RESET, "pca9546_reset");
|
||||
gpio_direction_output(I2C1_PCA9546_RESET, 1);
|
||||
|
||||
/* Select VSEL0 on voltage regulators */
|
||||
gpio_request(ARM_DRAM_VSEL, "arm_dram_vsel");
|
||||
gpio_direction_output(ARM_DRAM_VSEL, 0);
|
||||
gpio_request(DRAM_1P1_VSEL, "dram_1p1_vsel");
|
||||
gpio_direction_output(DRAM_1P1_VSEL, 0);
|
||||
gpio_request(SOC_GPU_VPU_VSEL, "soc_gpu_vpu_vsel");
|
||||
gpio_direction_output(SOC_GPU_VPU_VSEL, 0);
|
||||
|
||||
/* Set mux to target ARM/DRAM regulator */
|
||||
i2c_write(I2C_MUX_ADDR, 1, 1, NULL, 0);
|
||||
/* .6 + .40 = 1.00 */
|
||||
val = 0x80 + 40;
|
||||
i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
|
||||
i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
|
||||
|
||||
/* Set mux to target DRAM regulator */
|
||||
i2c_write(I2C_MUX_ADDR, 2, 1, NULL, 0);
|
||||
/* .6 + .50 = 1.10 */
|
||||
val = 0x80 + 50;
|
||||
i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
|
||||
i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
|
||||
|
||||
/* Set mux to target SoC/GPU/VPU regulator */
|
||||
i2c_write(I2C_MUX_ADDR, 4, 1, NULL, 0);
|
||||
/* .6 + .30 = .90 */
|
||||
val = 0x80 + 30;
|
||||
i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
|
||||
i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
|
||||
|
||||
/* Set mux to target peripherals */
|
||||
i2c_write(I2C_MUX_ADDR, 8, 1, NULL, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
puts("Normal Boot\n");
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_LOAD_FIT
|
||||
int board_fit_config_name_match(const char *name)
|
||||
{
|
||||
/* Just empty function now - can't decide what to choose */
|
||||
debug("%s: %s\n", __func__, name);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* Clear global data */
|
||||
memset((void *)gd, 0, sizeof(gd_t));
|
||||
|
||||
arch_cpu_init();
|
||||
|
||||
init_uart_clk(0);
|
||||
|
||||
board_early_init_f();
|
||||
|
||||
timer_init();
|
||||
|
||||
preloader_console_init();
|
||||
|
||||
/* Clear the BSS. */
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
|
||||
ret = spl_init();
|
||||
if (ret) {
|
||||
debug("spl_init() failed: %d\n", ret);
|
||||
hang();
|
||||
}
|
||||
|
||||
enable_tzc380();
|
||||
|
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
|
||||
|
||||
power_init_board();
|
||||
|
||||
/* DDR initialization */
|
||||
spl_dram_init();
|
||||
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
|
|
@ -12,4 +12,11 @@ config SYS_CONFIG_NAME
|
|||
config IMX_CONFIG
|
||||
default "board/storopack/smegw01/imximage.cfg"
|
||||
|
||||
config SYS_BOOT_LOCKED
|
||||
bool "Lock boot process to EMMC"
|
||||
default y
|
||||
help
|
||||
Say N here if you want to boot from eMMC and SD.
|
||||
Say Y to boot from eMMC.
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -14,9 +14,11 @@
|
|||
#include <asm/io.h>
|
||||
#include <common.h>
|
||||
#include <env.h>
|
||||
#include <env_internal.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/setup.h>
|
||||
#include <asm/bootm.h>
|
||||
#include <mmc.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
|
@ -80,6 +82,7 @@ int board_init(void)
|
|||
int board_late_init(void)
|
||||
{
|
||||
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
|
||||
unsigned char eth1addr[6];
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
|
||||
|
||||
|
|
@ -91,5 +94,35 @@ int board_late_init(void)
|
|||
*/
|
||||
clrsetbits_le16(&wdog->wcr, 0, 0x10);
|
||||
|
||||
/* Get the second MAC address */
|
||||
imx_get_mac_from_fuse(1, eth1addr);
|
||||
if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr))
|
||||
eth_env_set_enetaddr("eth1addr", eth1addr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint board_mmc_get_env_part(struct mmc *mmc)
|
||||
{
|
||||
uint part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
|
||||
|
||||
if (part == 7)
|
||||
part = 0;
|
||||
return part;
|
||||
}
|
||||
|
||||
enum env_location env_get_location(enum env_operation op, int prio)
|
||||
{
|
||||
if (op == ENVOP_SAVE || op == ENVOP_ERASE)
|
||||
return ENVL_MMC;
|
||||
|
||||
switch (prio) {
|
||||
case 0:
|
||||
return ENVL_NOWHERE;
|
||||
|
||||
case 1:
|
||||
return ENVL_MMC;
|
||||
}
|
||||
|
||||
return ENVL_UNKNOWN;
|
||||
}
|
||||
|
|
|
|||
89
board/storopack/smegw01/smegw01.env
Normal file
89
board/storopack/smegw01/smegw01.env
Normal file
|
|
@ -0,0 +1,89 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
#ifdef CONFIG_SYS_BOOT_LOCKED
|
||||
#define SETUP_BOOT_MENU setup_boot_menu=setenv bootmenu_0 eMMC=run bootcmd
|
||||
#else
|
||||
#define SETUP_BOOT_MENU setup_boot_menu= \
|
||||
if test "${mmcdev}" = 1; then \
|
||||
setenv emmc_priority 0; \
|
||||
setenv sd_priority 1; \
|
||||
else setenv emmc_priority 1; \
|
||||
setenv sd_priority 0; \
|
||||
fi; \
|
||||
setenv bootmenu_${emmc_priority} eMMC=run boot_emmc; \
|
||||
setenv bootmenu_${sd_priority} SD=run boot_sd;
|
||||
#endif
|
||||
|
||||
altbootcmd=
|
||||
echo Performing rollback...;
|
||||
if test "${mmcpart_committed}" = 1; then
|
||||
setenv mmcpart 2;
|
||||
setenv mmcpart_committed 2;
|
||||
else
|
||||
setenv mmcpart 1;
|
||||
setenv mmcpart_committed 1;
|
||||
fi;
|
||||
setenv bootcount 0;
|
||||
setenv upgrade_available;
|
||||
setenv ustate 3;
|
||||
saveenv;
|
||||
run bootcmd;
|
||||
boot_emmc=setenv mmcdev_wanted 1; run persist_mmcdev; run bootcmd;
|
||||
boot_sd=setenv mmcdev_wanted 0; run persist_mmcdev; run bootcmd;
|
||||
bootcmd=run finduuid; run distro_bootcmd
|
||||
bootdelay=2
|
||||
bootlimit=3
|
||||
bootm_size=0x10000000
|
||||
commit_mmc=
|
||||
if test "${ustate}" = 1 -a "${mmcpart}" != "${mmcpart_committed}"; then
|
||||
setenv mmcpart_committed ${mmcpart};
|
||||
saveenv;
|
||||
fi;
|
||||
console=ttymxc0
|
||||
fdt_addr=0x83000000
|
||||
fdtfile=imx7d-smegw01.dtb
|
||||
fit_addr=0x88000000
|
||||
image=fitImage
|
||||
loadaddr=0x80800000
|
||||
loadbootpart=mmc partconf 1 boot_part
|
||||
loadimage=load mmc ${mmcdev}:${gpt_partition_entry} ${fit_addr} boot/${image}
|
||||
loadpart=gpt setenv mmc ${mmcdev} rootfs-${mmcpart_committed}
|
||||
mmcargs=
|
||||
setenv bootargs console=${console},${baudrate} root=/dev/mmcblk${mmcdev}p${gpt_partition_entry} rootwait rw SM_ROOT_DEV=${mmcdev} SM_ROOT_PART=${gpt_partition_entry} SM_BOOT_PART=${boot_part}
|
||||
mmcboot=
|
||||
echo Booting...;
|
||||
echo mmcdev: ${mmcdev};
|
||||
run commit_mmc;
|
||||
echo mmcpart: ${mmcpart_committed};
|
||||
run loadpart;
|
||||
echo gptpart: ${gpt_partition_entry};
|
||||
run loadbootpart;
|
||||
if run loadimage; then
|
||||
;
|
||||
else
|
||||
run altbootcmd;
|
||||
fi;
|
||||
run mmcargs;
|
||||
if bootm ${fit_addr}; then
|
||||
;
|
||||
else
|
||||
run altbootcmd;
|
||||
fi;
|
||||
mmcdev=1
|
||||
mmcpart=1
|
||||
mmcpart_committed=1
|
||||
persist_mmcdev=
|
||||
if test "${mmcdev}" != "${mmcdev_wanted}"; then
|
||||
setenv mmcdev "${mmcdev_wanted}";
|
||||
saveenv;
|
||||
fi;
|
||||
setup_boot_menu=
|
||||
if test "${mmcdev}" = 1; then
|
||||
setenv emmc_priority 0;
|
||||
setenv sd_priority 1;
|
||||
else
|
||||
setenv emmc_priority 1;
|
||||
setenv sd_priority 0;
|
||||
fi;
|
||||
setenv bootmenu_${emmc_priority} eMMC=run boot_emmc;
|
||||
setenv bootmenu_${sd_priority} SD=run boot_sd;
|
||||
SETUP_BOOT_MENU
|
||||
|
|
@ -559,7 +559,7 @@ config BOARD_TYPES
|
|||
|
||||
config DISPLAY_CPUINFO
|
||||
bool "Display information about the CPU during start up"
|
||||
default y if ARC|| ARM || NIOS2 || X86 || XTENSA || M68K
|
||||
default y if ARC || ARM || NIOS2 || X86 || XTENSA || M68K
|
||||
help
|
||||
Display information about the CPU that U-Boot is running on
|
||||
when U-Boot starts up. The function print_cpuinfo() is called
|
||||
|
|
|
|||
107
configs/imx8mq_reform2_defconfig
Normal file
107
configs/imx8mq_reform2_defconfig
Normal file
|
|
@ -0,0 +1,107 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_IMX8M=y
|
||||
CONFIG_TEXT_BASE=0x40200000
|
||||
CONFIG_SYS_MALLOC_LEN=0x600000
|
||||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_ENV_SIZE=0x1000
|
||||
CONFIG_ENV_OFFSET=0x400000
|
||||
CONFIG_SYS_I2C_MXC_I2C1=y
|
||||
CONFIG_SYS_I2C_MXC_I2C2=y
|
||||
CONFIG_SYS_I2C_MXC_I2C3=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx8mq-mnt-reform2"
|
||||
CONFIG_SPL_TEXT_BASE=0x7E1000
|
||||
CONFIG_TARGET_IMX8MQ_REFORM2=y
|
||||
CONFIG_SYS_PROMPT="u-boot=> "
|
||||
CONFIG_SPL_MMC=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL_DRIVERS_MISC=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_IMX_BOOTAUX=y
|
||||
CONFIG_SYS_LOAD_ADDR=0x40480000
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_REMAKE_ELF=y
|
||||
CONFIG_SYS_MONITOR_LEN=524288
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_USE_SPL_FIT_GENERATOR is not set
|
||||
CONFIG_OF_SYSTEM_SETUP=y
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="freescale/imx8mq-mnt-reform2.dtb"
|
||||
CONFIG_CONSOLE_MUX=y
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_BOARD_LATE_INIT=y
|
||||
CONFIG_SPL_MAX_SIZE=0x1f000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x180000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x2000
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_SPL_STACK=0x187ff0
|
||||
CONFIG_SYS_SPL_MALLOC=y
|
||||
CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
|
||||
CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
|
||||
CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_SPL_POWER=y
|
||||
CONFIG_SPL_WATCHDOG=y
|
||||
CONFIG_SYS_MAXARGS=64
|
||||
CONFIG_SYS_PBSIZE=1050
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
# CONFIG_CMD_EXPORTENV is not set
|
||||
# CONFIG_CMD_IMPORTENV is not set
|
||||
# CONFIG_CMD_CRC32 is not set
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_FUSE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_MDIO is not set
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_SYS_MMC_ENV_DEV=1
|
||||
CONFIG_USE_ETHPRIME=y
|
||||
CONFIG_ETHPRIME="FEC"
|
||||
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
|
||||
CONFIG_MXC_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SPL_SYS_I2C_LEGACY=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_FSL_USDHC=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_FEC_MXC=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_PHY=y
|
||||
CONFIG_PHY_IMX8MQ_USB=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX8M=y
|
||||
CONFIG_SPL_POWER_LEGACY=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_IMX8M_POWER_DOMAIN=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_SPL_POWER_I2C=y
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_KEYBOARD=y
|
||||
129
configs/imx8qm_dmsse20a1_defconfig
Normal file
129
configs/imx8qm_dmsse20a1_defconfig
Normal file
|
|
@ -0,0 +1,129 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SPL_SYS_ICACHE_OFF=y
|
||||
CONFIG_SPL_SYS_DCACHE_OFF=y
|
||||
CONFIG_ARCH_IMX8=y
|
||||
CONFIG_TEXT_BASE=0x80020000
|
||||
CONFIG_SPL_GPIO_SUPPORT=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_NR_DRAM_BANKS=4
|
||||
CONFIG_SYS_MALLOC_LEN=0x2800000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x4000
|
||||
CONFIG_SYS_MMC_IMG_LOAD_PART=0
|
||||
CONFIG_TARGET_IMX8QM_DMSSE20_A1=y
|
||||
CONFIG_SPL_MMC=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL_DRIVERS_MISC=y
|
||||
CONFIG_ENV_OFFSET=0x80000
|
||||
CONFIG_ENV_SECT_SIZE=0x20000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SYS_LOAD_ADDR=0x80280000
|
||||
CONFIG_SYS_MEMTEST_START=0xA0000000
|
||||
CONFIG_SYS_MEMTEST_END=0xC0000000
|
||||
CONFIG_REMAKE_ELF=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_SIGNATURE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_USE_SPL_FIT_GENERATOR is not set
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_CI_UDC=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_EVENT=y
|
||||
CONFIG_DM_EVENT=y
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
|
||||
CONFIG_LOG=y
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x00128000
|
||||
CONFIG_SPL_MAX_SIZE=0x1f000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x1000
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
CONFIG_SPL_SEPARATE_BSS=y
|
||||
CONFIG_SPL_POWER_SUPPORT=y
|
||||
CONFIG_SPL_POWER_DOMAIN=y
|
||||
CONFIG_SPL_WATCHDOG_SUPPORT=y
|
||||
CONFIG_SYS_BOOTM_LEN=0x04000000
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_IMX_BOOTAUX=y
|
||||
CONFIG_FS_FAT=y
|
||||
CONFIG_FS_EXT4=y
|
||||
# CONFIG_BOOTM_NETBSD is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS400_SUPPORT=y
|
||||
CONFIG_MMC_BROKEN_CD=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_FUSE=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx8qm-dmsse20-a1"
|
||||
CONFIG_ENV_SOURCE_FILE="imx8qm_dmsse20-a1"
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SYS_MMC_ENV_DEV=2
|
||||
CONFIG_SYS_MMC_ENV_PART=0
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_SPL_CLK=y
|
||||
CONFIG_CLK_IMX8=y
|
||||
CONFIG_CPU=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_FSL_ESDHC_IMX=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_FSL_USDHC=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_ADDR_ENABLE=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_DM_ETH=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
CONFIG_FEC_MXC_SHARE_MDIO=y
|
||||
CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
|
||||
CONFIG_FEC_MXC=y
|
||||
CONFIG_FEC1_ENET_DEV=0
|
||||
CONFIG_ETHPRIME="eth0"
|
||||
CONFIG_FEC1_MXC_PHYADDR=0x4
|
||||
CONFIG_FEC2_ENET_DEV=1
|
||||
CONFIG_ETHPRIME1="eth1"
|
||||
CONFIG_FEC2_MXC_PHYADDR=0x4
|
||||
CONFIG_MII=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX8=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_IMX8_POWER_DOMAIN=y
|
||||
CONFIG_IMX_SMMU=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_SPL_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_SPL_DM_REGULATOR_GPIO=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_FSL_LPUART=y
|
||||
CONFIG_BAUDRATE=115200
|
||||
CONFIG_MISC=y
|
||||
CONFIG_SMC_FUSE=y
|
||||
CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
|
||||
CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_SPL_TINY_MEMSET=y
|
||||
CONFIG_AHAB_BOOT=y
|
||||
CONFIG_SYS_I2C_IMX_LPI2C=y
|
||||
CONFIG_DM_RTC=y
|
||||
CONFIG_RTC_RV8803=y
|
||||
CONFIG_CMD_DATE=y
|
||||
|
|
@ -76,6 +76,7 @@ CONFIG_DM_REGULATOR=y
|
|||
CONFIG_DM_REGULATOR_PFUZE100=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_MAX_CONTROLLER_COUNT=2
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@ CONFIG_ENV_OFFSET=0x100000
|
|||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx7d-smegw01"
|
||||
CONFIG_TARGET_SMEGW01=y
|
||||
# CONFIG_SYS_BOOT_LOCKED is not set
|
||||
CONFIG_ENV_OFFSET_REDUND=0x110000
|
||||
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
|
||||
# CONFIG_ARMV7_VIRT is not set
|
||||
|
|
@ -17,19 +18,27 @@ CONFIG_SYS_MEMTEST_START=0x80000000
|
|||
CONFIG_SYS_MEMTEST_END=0xa0000000
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_AUTOBOOT_MENU_SHOW=y
|
||||
# CONFIG_BOOTSTD is not set
|
||||
# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
|
||||
CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE=y
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="if run loadimage; then run mmcboot; fi; "
|
||||
CONFIG_BOOTCOMMAND="if test \"${bootcount}\" -gt \"${bootlimit}\"; then run altbootcmd; else if test \"${ustate}\" = 1; then setenv upgrade_available 1; saveenv; fi; run mmcboot; fi;"
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_PREBOOT="run setup_boot_menu;"
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_SYS_MAXARGS=32
|
||||
CONFIG_SYS_PBSIZE=532
|
||||
# CONFIG_CMD_BOOTD is not set
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_BOOTMENU=y
|
||||
# CONFIG_CMD_IMI is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_UNZIP=y
|
||||
CONFIG_CMD_DFU=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PART=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
|
|
@ -38,13 +47,20 @@ CONFIG_CMD_EXT2=y
|
|||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_SQUASHFS=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_NOWHERE=y
|
||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_SYS_MMC_ENV_DEV=1
|
||||
CONFIG_ENV_WRITEABLE_LIST=y
|
||||
CONFIG_ENV_ACCESS_IGNORE_FORCE=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_BOUNCE_BUFFER=y
|
||||
CONFIG_BOOTCOUNT_LIMIT=y
|
||||
CONFIG_BOOTCOUNT_ENV=y
|
||||
CONFIG_DFU_MMC=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
|
|
|
|||
58
doc/board/advantech/imx8qm-dmsse20-a1.rst
Normal file
58
doc/board/advantech/imx8qm-dmsse20-a1.rst
Normal file
|
|
@ -0,0 +1,58 @@
|
|||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
NXP i.MX8QM DMSSE20-a1 board
|
||||
============================
|
||||
|
||||
Quick Start
|
||||
-----------
|
||||
|
||||
- Build the ARM Trusted firmware binary
|
||||
- Get scfw_tcm.bin and ahab-container.img
|
||||
- Get imx-mkimage
|
||||
- Build U-Boot
|
||||
- Flash the binary into the SD card
|
||||
- Boot
|
||||
|
||||
Get and Build the ARM Trusted Firmware
|
||||
--------------------------------------
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ git clone https://github.com/nxp-imx/imx-atf
|
||||
$ cd imx-atf/
|
||||
$ git checkout lf-5.10.72-2.2.0 -b lf-5.10.72-2.2.0
|
||||
$ make PLAT=imx8qm bl31
|
||||
$ cp build/imx8qm/release/bl31.bin $(builddir)
|
||||
|
||||
Get scfw_tcm.bin and ahab-container.img
|
||||
---------------------------------------
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.11.0.bin
|
||||
$ chmod +x imx-sc-firmware-1.11.0.bin
|
||||
$ ./imx-sc-firmware-1.11.0.bin
|
||||
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-seco-3.8.5.bin
|
||||
$ chmod +x imx-seco-3.8.5.bin
|
||||
$ ./imx-seco-3.8.5.bin
|
||||
|
||||
Or use this to avoid running random scripts from the internet,
|
||||
but note that you must agree to the license the script displays:
|
||||
|
||||
.. code-block:: bash
|
||||
|
||||
$ dd if=imx-sc-firmware-1.11.0.bin of=imx-sc-firmware-1.11.0.tar.bz2 bs=42757 skip=1
|
||||
$ tar -xf imx-sc-firmware-1.11.0.tar.bz2
|
||||
$ cp imx-sc-firmware-1.11.0/mx8qm-val-scfw-tcm.bin $(builddir)
|
||||
$ dd if=imx-seco-3.8.5.bin of=imx-seco-3.8.5.tar.bz2 bs=43978 skip=1
|
||||
$ tar -xf imx-seco-3.8.5.tar.bz2
|
||||
$ cp imx-seco-3.8.5/firmware/seco/mx8qmb0-ahab-container.img $(builddir)
|
||||
|
||||
Build U-Boot
|
||||
------------
|
||||
.. code-block:: bash
|
||||
|
||||
$ export ATF_LOAD_ADDR=0x80000000
|
||||
$ export BL33_LOAD_ADDR=0x80020000
|
||||
$ make imx8qm_dmsse20a1_defconfig
|
||||
$ make
|
||||
|
|
@ -7,3 +7,4 @@ Advantech
|
|||
:maxdepth: 2
|
||||
|
||||
imx8qm-rom7720-a1.rst
|
||||
imx8qm-dmsse20-a1.rst
|
||||
|
|
|
|||
|
|
@ -703,6 +703,10 @@ static int ehci_usb_probe(struct udevice *dev)
|
|||
usb_internal_phy_clock_gate(priv->phy_addr, 1);
|
||||
usb_phy_enable(ehci, priv->phy_addr);
|
||||
#endif
|
||||
#else
|
||||
ret = generic_setup_phy(dev, &priv->phy, 0);
|
||||
if (ret)
|
||||
goto err_regulator;
|
||||
#endif
|
||||
|
||||
#if CONFIG_IS_ENABLED(DM_REGULATOR)
|
||||
|
|
@ -725,12 +729,6 @@ static int ehci_usb_probe(struct udevice *dev)
|
|||
|
||||
mdelay(10);
|
||||
|
||||
#if defined(CONFIG_PHY)
|
||||
ret = generic_setup_phy(dev, &priv->phy, 0);
|
||||
if (ret)
|
||||
goto err_regulator;
|
||||
#endif
|
||||
|
||||
hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);
|
||||
hcor = (struct ehci_hcor *)((uintptr_t)hccr +
|
||||
HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
|
||||
|
|
|
|||
67
include/configs/imx8mq_reform2.h
Normal file
67
include/configs/imx8mq_reform2.h
Normal file
|
|
@ -0,0 +1,67 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#ifndef __IMX8M_REFORM2_H
|
||||
#define __IMX8M_REFORM2_H
|
||||
|
||||
#include <linux/sizes.h>
|
||||
#include <linux/stringify.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
|
||||
|
||||
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
|
||||
#define CFG_MALLOC_F_ADDR 0x182000
|
||||
/* For RAW image gives a error info not panic */
|
||||
#endif
|
||||
|
||||
/* ENET Config */
|
||||
/* ENET1 */
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
#define CFG_FEC_MXC_PHYADDR 4
|
||||
#endif
|
||||
|
||||
#define BOOT_TARGET_DEVICES(func) \
|
||||
func(MMC, mmc, 1) \
|
||||
func(MMC, mmc, 0) \
|
||||
func(USB, usb, 0) \
|
||||
func(DHCP, dhcp, na)
|
||||
|
||||
#include <config_distro_bootcmd.h>
|
||||
|
||||
/* Initial environment variables */
|
||||
#define CFG_EXTRA_ENV_SETTINGS \
|
||||
BOOTENV \
|
||||
"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
|
||||
"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
|
||||
"image=Image\0" \
|
||||
"console=ttymxc0,115200\0" \
|
||||
"fdt_addr_r=0x43000000\0" \
|
||||
"ramdisk_addr_r=0x44000000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"fdtfile=imx8mq-mnt-reform2.dtb\0" \
|
||||
"initrd_addr=0x43800000\0" \
|
||||
"bootm_size=0x10000000\0" \
|
||||
"mmcpart=1\0" \
|
||||
"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
|
||||
"stdin=serial,usbkbd\0"
|
||||
|
||||
/* Link Definitions */
|
||||
|
||||
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
|
||||
#define CFG_SYS_INIT_RAM_SIZE 0x80000
|
||||
|
||||
|
||||
#define CFG_SYS_SDRAM_BASE 0x40000000
|
||||
#define PHYS_SDRAM 0x40000000
|
||||
#define PHYS_SDRAM_SIZE 0x100000000 /* 4 GiB DDR */
|
||||
|
||||
#define CFG_MXC_UART_BASE UART_BASE_ADDR(1)
|
||||
|
||||
#define CFG_SYS_FSL_USDHC_NUM 2
|
||||
#define CFG_SYS_FSL_ESDHC_ADDR 0
|
||||
|
||||
#endif
|
||||
48
include/configs/imx8qm_dmsse20.h
Normal file
48
include/configs/imx8qm_dmsse20.h
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2017-2019 NXP
|
||||
* Copyright 2019-2023 Kococonnector GmbH
|
||||
*/
|
||||
|
||||
#ifndef __IMX8QM_DMSSE20_H
|
||||
#define __IMX8QM_DMSSE20_H
|
||||
|
||||
#include <linux/sizes.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
/* Flat Device Tree Definitions */
|
||||
|
||||
#define CFG_SYS_FSL_ESDHC_ADDR 0
|
||||
#define USDHC1_BASE_ADDR 0x5B010000
|
||||
#define USDHC2_BASE_ADDR 0x5B020000
|
||||
#define USDHC3_BASE_ADDR 0x5B030000
|
||||
|
||||
#define FEC_QUIRK_ENET_MAC
|
||||
|
||||
#define IMX_FEC_BASE 0x5B040000
|
||||
/* FEC1 */
|
||||
#define IMX_FEC1_BASE 0x5B040000
|
||||
/* FEC2 */
|
||||
#define IMX_FEC2_BASE 0x5B050000
|
||||
|
||||
#ifdef CONFIG_NAND_BOOT
|
||||
#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) "
|
||||
#else
|
||||
#define MFG_NAND_PARTITION ""
|
||||
#endif
|
||||
|
||||
/* Incorporate settings into the U-Boot environment */
|
||||
#define CFG_EXTRA_ENV_SETTINGS
|
||||
|
||||
#define CFG_SYS_FSL_USDHC_NUM 2
|
||||
|
||||
#define CFG_SYS_SDRAM_BASE 0x080000000
|
||||
#define PHYS_SDRAM_1 0x080000000
|
||||
#define PHYS_SDRAM_2 0x880000000
|
||||
#define PHYS_SDRAM_1_SIZE 0x080000000 /* 2 GB */
|
||||
#define PHYS_SDRAM_2_SIZE 0x180000000 /* 6 GB */
|
||||
|
||||
/* Generic Timer Definitions */
|
||||
#define COUNTER_FREQUENCY 8000000 /* 8MHz */
|
||||
|
||||
#endif /* __IMX8QM_DMSSE20_H */
|
||||
|
|
@ -17,23 +17,25 @@
|
|||
/* MMC Config*/
|
||||
#define CFG_SYS_FSL_ESDHC_ADDR 0
|
||||
|
||||
#define CFG_EXTRA_ENV_SETTINGS \
|
||||
"image=zImage\0" \
|
||||
"console=ttymxc0\0" \
|
||||
"fdtfile=imx7d-smegw01.dtb\0" \
|
||||
"fdt_addr=0x83000000\0" \
|
||||
"bootm_size=0x10000000\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcpart=1\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=/dev/mmcblk0p${mmcpart} rootwait rw\0" \
|
||||
"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image}\0" \
|
||||
"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if run loadfdt; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"fi;\0" \
|
||||
/* default to no extra bootparams, we need an empty define for stringification*/
|
||||
#ifndef EXTRA_BOOTPARAMS
|
||||
#define EXTRA_BOOTPARAMS
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_BOOT_LOCKED
|
||||
#define EXTRA_ENV_FLAGS
|
||||
#else
|
||||
#define EXTRA_ENV_FLAGS "mmcdev:dw,"
|
||||
#endif
|
||||
|
||||
#define CFG_ENV_FLAGS_LIST_STATIC \
|
||||
"mmcpart:dw," \
|
||||
"mmcpart_committed:dw," \
|
||||
"ustate:dw," \
|
||||
"bootcount:dw," \
|
||||
"bootlimit:dw," \
|
||||
"upgrade_available:dw," \
|
||||
EXTRA_ENV_FLAGS
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
|
||||
|
|
|
|||
Loading…
Reference in a new issue