Merge branch '2019-09-13-ti-imports'
- Assorted K3 bugfixes. - Assorted DM enablements, dead code removal.
This commit is contained in:
Tom Rini
commit
23b93e33ad
14 changed files with 482 additions and 99 deletions
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@ -302,7 +302,8 @@ dtb-$(CONFIG_AM33XX) += \
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dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \
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am43x-epos-evm.dtb \
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am437x-idk-evm.dtb \
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am4372-generic.dtb
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am4372-generic.dtb \
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am437x-cm-t43.dtb
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dtb-$(CONFIG_TARGET_AM3517_EVM) += am3517-evm.dtb
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dtb-$(CONFIG_TI816X) += dm8168-evm.dtb
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dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
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420
arch/arm/dts/am437x-cm-t43.dts
Normal file
420
arch/arm/dts/am437x-cm-t43.dts
Normal file
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@ -0,0 +1,420 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/
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*/
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/dts-v1/;
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#include <dt-bindings/pinctrl/am43xx.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "am4372.dtsi"
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/ {
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model = "CompuLab CM-T43";
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compatible = "compulab,am437x-cm-t43", "ti,am4372", "ti,am43";
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leds {
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compatible = "gpio-leds";
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ledb {
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label = "cm-t43:green";
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gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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vmmc_3v3: fixedregulator-v3_3 {
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compatible = "regulator-fixed";
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regulator-name = "vmmc_3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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enable-active-high;
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};
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};
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&am43xx_pinmux {
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pinctrl-names = "default";
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pinctrl-0 = <&cm_t43_led_pins>;
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cm_t43_led_pins: cm_t43_led_pins {
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pinctrl-single,pins = <
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AM4372_IOPAD(0xa78, MUX_MODE7)
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>;
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};
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i2c0_pins: i2c0_pins {
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pinctrl-single,pins = <
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AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
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AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
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>;
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};
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emmc_pins: emmc_pins {
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pinctrl-single,pins = <
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AM4372_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad8.mmc1_dat0 */
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AM4372_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad9.mmc1_dat1 */
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AM4372_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad10.mmc1_dat2 */
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AM4372_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad11.mmc1_dat3 */
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AM4372_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad12.mmc1_dat4 */
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AM4372_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad13.mmc1_dat5 */
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AM4372_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad14.mmc1_dat6 */
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AM4372_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad15.mmc1_dat7 */
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AM4372_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
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AM4372_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
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>;
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};
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spi0_pins: pinmux_spi0_pins {
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pinctrl-single,pins = <
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AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_sclk.spi0_sclk */
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AM4372_IOPAD(0x954, PIN_INPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */
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AM4372_IOPAD(0x958, PIN_OUTPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */
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AM4372_IOPAD(0x95C, PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
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>;
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};
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nand_flash_x8: nand_flash_x8 {
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pinctrl-single,pins = <
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AM4372_IOPAD(0x800, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
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AM4372_IOPAD(0x804, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
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AM4372_IOPAD(0x808, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
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AM4372_IOPAD(0x80c, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
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AM4372_IOPAD(0x810, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
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AM4372_IOPAD(0x814, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
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AM4372_IOPAD(0x818, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
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AM4372_IOPAD(0x81c, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
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AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)
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AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE0)
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AM4372_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE0)
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AM4372_IOPAD(0x898, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
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AM4372_IOPAD(0x894, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
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AM4372_IOPAD(0x890, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
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AM4372_IOPAD(0x89c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
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>;
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};
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cpsw_default: cpsw_default {
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pinctrl-single,pins = <
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/* Slave 1 */
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AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
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AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */
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AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
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AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
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AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
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AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
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AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
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AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
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AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */
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AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */
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AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
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AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
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AM4372_IOPAD(0xa74, MUX_MODE3)
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/* Slave 2 */
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AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.txen */
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AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rxctl */
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AM4372_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.txd3 */
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AM4372_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.txd2 */
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AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.txd1 */
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AM4372_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.txd0 */
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AM4372_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.tclk */
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AM4372_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rclk */
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AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rxd3 */
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AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rxd2 */
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AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rxd1 */
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AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rxd0 */
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AM4372_IOPAD(0xa38, MUX_MODE7)
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>;
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};
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davinci_mdio_default: davinci_mdio_default {
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pinctrl-single,pins = <
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/* MDIO */
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AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
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AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
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>;
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};
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};
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&gpmc {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&nand_flash_x8>;
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ranges = <0 0 0x08000000 0x1000000>;
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nand@0,0 {
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compatible = "ti,omap2-nand";
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reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
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interrupt-parent = <&gpmc>;
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interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
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<1 IRQ_TYPE_NONE>; /* termcount */
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ti,nand-ecc-opt = "bch8";
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ti,elm-id = <&elm>;
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nand-bus-width = <8>;
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gpmc,device-width = <1>;
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gpmc,sync-clk-ps = <0>;
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gpmc,cs-on-ns = <0>;
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gpmc,cs-rd-off-ns = <44>;
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gpmc,cs-wr-off-ns = <44>;
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gpmc,adv-on-ns = <6>;
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gpmc,adv-rd-off-ns = <34>;
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gpmc,adv-wr-off-ns = <44>;
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gpmc,we-on-ns = <0>;
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gpmc,we-off-ns = <40>;
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gpmc,oe-on-ns = <0>;
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gpmc,oe-off-ns = <54>;
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gpmc,access-ns = <64>;
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gpmc,rd-cycle-ns = <82>;
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gpmc,wr-cycle-ns = <82>;
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gpmc,bus-turnaround-ns = <0>;
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gpmc,cycle2cycle-delay-ns = <0>;
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gpmc,clk-activation-ns = <0>;
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gpmc,wr-access-ns = <40>;
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gpmc,wr-data-mux-bus-ns = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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/* MTD partition table */
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partition@0 {
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label = "kernel";
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reg = <0x0 0x00980000>;
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};
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partition@980000 {
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label = "dtb";
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reg = <0x00980000 0x00080000>;
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};
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partition@a00000 {
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label = "rootfs";
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reg = <0x00a00000 0x0>;
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};
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};
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};
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&i2c0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins>;
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clock-frequency = <100000>;
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tps65218: tps65218@24 {
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compatible = "ti,tps65218";
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reg = <0x24>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* NMIn */
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interrupt-parent = <&gic>;
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interrupt-controller;
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#interrupt-cells = <2>;
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dcdc1: regulator-dcdc1 {
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regulator-name = "vdd_core";
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regulator-min-microvolt = <912000>;
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regulator-max-microvolt = <1144000>;
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regulator-boot-on;
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regulator-always-on;
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};
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dcdc2: regulator-dcdc2 {
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regulator-name = "vdd_mpu";
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regulator-min-microvolt = <912000>;
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regulator-max-microvolt = <1378000>;
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regulator-boot-on;
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regulator-always-on;
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};
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dcdc3: regulator-dcdc3 {
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regulator-name = "vdcdc3";
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regulator-suspend-enable;
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <1500000>;
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regulator-boot-on;
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regulator-always-on;
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};
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dcdc5: regulator-dcdc5 {
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regulator-name = "v1_0bat";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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dcdc6: regulator-dcdc6 {
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regulator-name = "v1_8bat";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo1: regulator-ldo1 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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eeprom_module: at24@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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pagesize = <16>;
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};
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};
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&gpio0 {
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status = "okay";
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};
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&gpio1 {
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status = "okay";
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};
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&gpio2 {
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status = "okay";
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};
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&gpio3 {
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status = "okay";
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};
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&gpio4 {
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status = "okay";
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};
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&gpio5 {
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status = "okay";
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};
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&mmc2 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&emmc_pins>;
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vmmc-supply = <&vmmc_3v3>;
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bus-width = <8>;
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ti,non-removable;
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};
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&spi0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_pins>;
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dmas = <&edma 16 0
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&edma 17 0>;
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dma-names = "tx0", "rx0";
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flash: w25q64cvzpig@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <20000000>;
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partition@0 {
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label = "uboot";
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reg = <0x0 0xc0000>;
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};
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partition@c0000 {
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label = "uboot environment";
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reg = <0xc0000 0x40000>;
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};
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partition@100000 {
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label = "reserved";
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reg = <0x100000 0x100000>;
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};
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};
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};
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&mac {
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pinctrl-names = "default";
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pinctrl-0 = <&cpsw_default>;
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dual_emac = <1>;
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status = "okay";
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};
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&davinci_mdio {
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pinctrl-names = "default";
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pinctrl-0 = <&davinci_mdio_default>;
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status = "okay";
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ethphy0: ethernet-phy@0 {
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reg = <0>;
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};
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ethphy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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&cpsw_emac0 {
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phy-handle = <ðphy0>;
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phy-mode = "rgmii-txid";
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dual_emac_res_vlan = <1>;
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};
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&cpsw_emac1 {
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phy-handle = <ðphy1>;
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phy-mode = "rgmii-txid";
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dual_emac_res_vlan = <2>;
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};
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&dwc3_1 {
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status = "okay";
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};
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&usb2_phy1 {
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status = "okay";
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};
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&usb1 {
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dr_mode = "host";
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status = "okay";
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};
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&dwc3_2 {
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status = "okay";
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};
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&usb2_phy2 {
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status = "okay";
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};
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&usb2 {
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dr_mode = "host";
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status = "okay";
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interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
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||||
<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "peripheral", "host", "otg";
|
||||
};
|
||||
|
||||
&elm {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tscadc {
|
||||
status = "okay";
|
||||
tsc {
|
||||
ti,wires = <4>;
|
||||
ti,x-plate-resistance = <200>;
|
||||
ti,coordiante-readouts = <5>;
|
||||
ti,wire-config = <0x00 0x11 0x22 0x33>;
|
||||
};
|
||||
|
||||
adc {
|
||||
ti,adc-channels = <4 5 6 7>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpu {
|
||||
cpu0-supply = <&dcdc2>;
|
||||
operating-points = <1000000 1330000>,
|
||||
<800000 1260000>,
|
||||
<720000 1200000>,
|
||||
<600000 1100000>,
|
||||
<300000 950000>;
|
||||
};
|
||||
|
|
@ -32,7 +32,7 @@
|
|||
*
|
||||
* Datamanual Revisions:
|
||||
*
|
||||
* AM572x Silicon Revision 2.0: SPRS953B, Revised November 2016
|
||||
* AM572x Silicon Revision 2.0: SPRS953F, Revised May 2019
|
||||
* AM572x Silicon Revision 1.1: SPRS915R, Revised November 2016
|
||||
*
|
||||
*/
|
||||
|
|
@ -229,45 +229,45 @@
|
|||
|
||||
mmc3_pins_default: mmc3_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
|
||||
DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
|
||||
DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
|
||||
DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
|
||||
DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
|
||||
DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
|
||||
DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
|
||||
DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
|
||||
DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
|
||||
DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
|
||||
DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
|
||||
DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc3_pins_hs: mmc3_pins_hs {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
|
||||
DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
|
||||
DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
|
||||
DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
|
||||
DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
|
||||
DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
|
||||
DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
|
||||
DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
|
||||
DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
|
||||
DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
|
||||
DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
|
||||
DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc3_pins_sdr12: mmc3_pins_sdr12 {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
|
||||
DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
|
||||
DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
|
||||
DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
|
||||
DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
|
||||
DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
|
||||
DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
|
||||
DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
|
||||
DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
|
||||
DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
|
||||
DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
|
||||
DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc3_pins_sdr25: mmc3_pins_sdr25 {
|
||||
pinctrl-single,pins = <
|
||||
DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
|
||||
DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
|
||||
DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
|
||||
DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
|
||||
DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
|
||||
DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
|
||||
DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
|
||||
DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
|
||||
DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
|
||||
DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
|
||||
DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
|
||||
DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -22,11 +22,7 @@
|
|||
#define gpio_status() gpio_info()
|
||||
#endif
|
||||
#define GPIO_NAME_SIZE 20
|
||||
#if !defined(CONFIG_SOC_DA850)
|
||||
#define MAX_NUM_GPIOS 128
|
||||
#else
|
||||
#define MAX_NUM_GPIOS 144
|
||||
#endif
|
||||
#define GPIO_BANK(gp) (davinci_gpio_bank01 + ((gp) >> 5))
|
||||
|
||||
void gpio_info(void);
|
||||
|
|
|
|||
|
|
@ -219,10 +219,9 @@ u32 spl_boot_device(void)
|
|||
|
||||
void release_resources_for_core_shutdown(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
struct ti_sci_handle *ti_sci;
|
||||
struct ti_sci_dev_ops *dev_ops;
|
||||
struct ti_sci_proc_ops *proc_ops;
|
||||
struct ti_sci_handle *ti_sci = get_ti_sci_handle();
|
||||
struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
|
||||
struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
|
||||
int ret;
|
||||
u32 i;
|
||||
|
||||
|
|
@ -231,15 +230,6 @@ void release_resources_for_core_shutdown(void)
|
|||
AM6_DEV_MCU_RTI1,
|
||||
};
|
||||
|
||||
/* Get handle to Device Management and Security Controller (SYSFW) */
|
||||
ret = uclass_get_device_by_name(UCLASS_FIRMWARE, "dmsc", &dev);
|
||||
if (ret)
|
||||
panic("Failed to get handle to SYSFW (%d)\n", ret);
|
||||
|
||||
ti_sci = (struct ti_sci_handle *)(ti_sci_get_handle_from_sysfw(dev));
|
||||
dev_ops = &ti_sci->ops.dev_ops;
|
||||
proc_ops = &ti_sci->ops.proc_ops;
|
||||
|
||||
/* Iterate through list of devices to put (shutdown) */
|
||||
for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
|
||||
u32 id = put_device_ids[i];
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@ struct ti_sci_handle *get_ti_sci_handle(void)
|
|||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
ret = uclass_get_device_by_name(UCLASS_FIRMWARE, "dmsc", &dev);
|
||||
ret = uclass_get_device(UCLASS_FIRMWARE, 0, &dev);
|
||||
if (ret)
|
||||
panic("Failed to get SYSFW (%d)\n", ret);
|
||||
|
||||
|
|
|
|||
|
|
@ -11,25 +11,16 @@
|
|||
#include <linux/soc/ti/ti_sci_protocol.h>
|
||||
#include <mach/spl.h>
|
||||
#include <spl.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
|
||||
void board_fit_image_post_process(void **p_image, size_t *p_size)
|
||||
{
|
||||
struct udevice *dev;
|
||||
struct ti_sci_handle *ti_sci;
|
||||
struct ti_sci_proc_ops *proc_ops;
|
||||
struct ti_sci_handle *ti_sci = get_ti_sci_handle();
|
||||
struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
|
||||
u64 image_addr;
|
||||
u32 image_size;
|
||||
int ret;
|
||||
|
||||
/* Get handle to Device Management and Security Controller (SYSFW) */
|
||||
ret = uclass_get_device_by_name(UCLASS_FIRMWARE, "dmsc", &dev);
|
||||
if (ret) {
|
||||
printf("Failed to get handle to SYSFW (%d)\n", ret);
|
||||
hang();
|
||||
}
|
||||
ti_sci = (struct ti_sci_handle *)(ti_sci_get_handle_from_sysfw(dev));
|
||||
proc_ops = &ti_sci->ops.proc_ops;
|
||||
|
||||
image_addr = (uintptr_t)*p_image;
|
||||
|
||||
debug("Authenticating image at address 0x%016llx\n", image_addr);
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@ CONFIG_FIT_IMAGE_POST_PROCESS=y
|
|||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
|
||||
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_fit_${boot}; run get_overlaystring; run run_fit"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_SPL_TEXT_BASE=0x80080000
|
||||
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||
|
|
|
|||
|
|
@ -32,6 +32,8 @@ CONFIG_SPL_POWER_SUPPORT=y
|
|||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
|
||||
CONFIG_SYS_PROMPT="CM-T43 # "
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="am437x-cm-t43"
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_CMD_EEPROM=y
|
||||
CONFIG_CMD_EEPROM_LAYOUT=y
|
||||
|
|
@ -52,9 +54,13 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
|
|||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_BLK=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_MMC_OMAP_HS=y
|
||||
CONFIG_NAND=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_SPEED=48000000
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
|
|
@ -70,6 +76,7 @@ CONFIG_DM_SERIAL=y
|
|||
CONFIG_SPI=y
|
||||
CONFIG_OMAP3_SPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_OMAP_USB_PHY=y
|
||||
|
|
|
|||
|
|
@ -25,9 +25,10 @@ CONFIG_HUSH_PARSER=y
|
|||
CONFIG_CRC32_VERIFY=y
|
||||
# CONFIG_CMD_EEPROM is not set
|
||||
CONFIG_MX_CYCLIC=y
|
||||
CONFIG_CMD_DM=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
# CONFIG_CMD_GPIO is not set
|
||||
CONFIG_CMD_NAND=y
|
||||
# CONFIG_CMD_PINMUX is not set
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_CMD_DIAG=y
|
||||
|
|
@ -40,6 +41,8 @@ CONFIG_ENV_IS_IN_NAND=y
|
|||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DA8XX_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_DAVINCI=y
|
||||
CONFIG_DM_MMC=y
|
||||
|
|
@ -56,11 +59,14 @@ CONFIG_MII=y
|
|||
CONFIG_DRIVER_TI_EMAC=y
|
||||
CONFIG_PHY=y
|
||||
CONFIG_PHY_DA8XX_USB=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_SINGLE=y
|
||||
CONFIG_SPECIFY_CONSOLE_INDEX=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
# CONFIG_SPL_DM_USB is not set
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_DA8XX=y
|
||||
CONFIG_USB_MUSB_HOST=y
|
||||
|
|
|
|||
|
|
@ -366,8 +366,10 @@ void k3_nav_ringacc_ring_reset_dma(struct k3_nav_ring *ring, u32 occ)
|
|||
if (!ring || !(ring->flags & KNAV_RING_FLAG_BUSY))
|
||||
return;
|
||||
|
||||
if (!ring->parent->dma_ring_reset_quirk)
|
||||
if (!ring->parent->dma_ring_reset_quirk) {
|
||||
k3_nav_ringacc_ring_reset(ring);
|
||||
return;
|
||||
}
|
||||
|
||||
if (!occ)
|
||||
occ = ringacc_readl(&ring->rt->occ);
|
||||
|
|
|
|||
|
|
@ -94,11 +94,14 @@
|
|||
"done;\0" \
|
||||
"get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \
|
||||
"${bootdir}/${name_kern}\0" \
|
||||
"get_fit_mmc=load mmc ${bootpart} ${addr_fit} " \
|
||||
"${bootdir}/${name_fit}\0" \
|
||||
"partitions=" PARTS_DEFAULT
|
||||
|
||||
/* Incorporate settings into the U-Boot environment */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
DEFAULT_MMC_TI_ARGS \
|
||||
DEFAULT_FIT_TI_ARGS \
|
||||
EXTRA_ENV_AM65X_BOARD_SETTINGS \
|
||||
EXTRA_ENV_AM65X_BOARD_SETTINGS_MMC
|
||||
|
||||
|
|
|
|||
|
|
@ -13,8 +13,6 @@
|
|||
/*
|
||||
* Board
|
||||
*/
|
||||
#undef CONFIG_USE_SPIFLASH
|
||||
#undef CONFIG_SYS_USE_NOR
|
||||
|
||||
/*
|
||||
* SoC Configuration
|
||||
|
|
@ -104,21 +102,10 @@
|
|||
* Serial Driver info
|
||||
*/
|
||||
#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
|
||||
#if !defined(CONFIG_DM_SERIAL)
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
|
||||
#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
|
||||
#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
|
||||
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
|
||||
|
||||
#ifdef CONFIG_USE_SPIFLASH
|
||||
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000
|
||||
#endif
|
||||
|
||||
/*
|
||||
* I2C Configuration
|
||||
*/
|
||||
|
|
@ -168,24 +155,6 @@
|
|||
#define CONFIG_SPL_NAND_LOAD
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_USE_NOR
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
|
||||
#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
|
||||
#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3)
|
||||
#define CONFIG_ENV_SIZE (128 << 10)
|
||||
#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
|
||||
#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
|
||||
+ 3)
|
||||
#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USE_SPIFLASH
|
||||
#define CONFIG_ENV_SIZE (64 << 10)
|
||||
#define CONFIG_ENV_OFFSET (256 << 10)
|
||||
#define CONFIG_ENV_SECT_SIZE (64 << 10)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Network & Ethernet Configuration
|
||||
*/
|
||||
|
|
@ -244,12 +213,6 @@
|
|||
#define CONFIG_CLOCKS
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_NAND) && \
|
||||
!defined(CONFIG_SYS_USE_NOR) && \
|
||||
!defined(CONFIG_USE_SPIFLASH)
|
||||
#define CONFIG_ENV_SIZE (16 << 10)
|
||||
#endif
|
||||
|
||||
/* SD/MMC */
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_MMC
|
||||
|
|
@ -259,7 +222,6 @@
|
|||
#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_DIRECT_NOR_BOOT
|
||||
/* defines for SPL */
|
||||
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
|
||||
CONFIG_SYS_MALLOC_LEN)
|
||||
|
|
@ -267,7 +229,6 @@
|
|||
#define CONFIG_SPL_STACK 0x8001ff00
|
||||
#define CONFIG_SPL_MAX_FOOTPRINT 32768
|
||||
#define CONFIG_SPL_PAD_TO 32768
|
||||
#endif
|
||||
|
||||
/* additions for new relocation code, must added to all boards */
|
||||
#define CONFIG_SYS_SDRAM_BASE 0xc0000000
|
||||
|
|
|
|||
|
|
@ -55,7 +55,13 @@
|
|||
"addr_fit=0x90000000\0" \
|
||||
"name_fit=fitImage\0" \
|
||||
"update_to_fit=setenv loadaddr ${addr_fit}; setenv bootfile ${name_fit}\0" \
|
||||
"loadfit=run args_mmc; bootm ${loadaddr}#${fdtfile};\0" \
|
||||
"get_overlaystring=" \
|
||||
"for overlay in $overlay_files;" \
|
||||
"do;" \
|
||||
"setenv overlaystring ${overlaystring}'#'${overlay};" \
|
||||
"done;\0" \
|
||||
"run_fit=bootm ${loadaddr}#${fdtfile}${overlaystring}\0" \
|
||||
"loadfit=run args_mmc; run run_fit;\0" \
|
||||
|
||||
/*
|
||||
* DDR information. If the CONFIG_NR_DRAM_BANKS is not defined,
|
||||
|
|
|
|||
Loading…
Reference in a new issue