ddr: imx9: update the rank setting for multi fsp support
The rank setting flow should be updated to support multi fsp config. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Jacky Bai
Stefano Babic
parent
8e81e679db
commit
212a4e1961
1 changed files with 108 additions and 54 deletions
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@ -145,68 +145,122 @@ void get_trained_CDD(u32 fsp)
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g_cdd_ww_max[fsp] = cdd_cha_ww_max > cdd_chb_ww_max ? cdd_cha_ww_max : cdd_chb_ww_max;
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}
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void update_umctl2_rank_space_setting(unsigned int pstat_num)
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static u32 ddrc_get_fsp_reg_setting(struct dram_cfg_param *ddrc_cfg, unsigned int cfg_num, u32 reg)
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{
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unsigned int i;
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for (i = 0; i < cfg_num; i++) {
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if (reg == ddrc_cfg[i].reg)
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return ddrc_cfg[i].val;
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}
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return 0;
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}
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static void ddrc_update_fsp_reg_setting(struct dram_cfg_param *ddrc_cfg, int cfg_num,
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u32 reg, u32 val)
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{
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unsigned int i;
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for (i = 0; i < cfg_num; i++) {
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if (reg == ddrc_cfg[i].reg) {
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ddrc_cfg[i].val = val;
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return;
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}
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}
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}
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void update_umctl2_rank_space_setting(struct dram_timing_info *dram_timing, unsigned int pstat_num)
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{
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u32 tmp, tmp_t;
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u32 wwt, rrt, wrt, rwt;
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u32 ext_wwt, ext_rrt, ext_wrt, ext_rwt;
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u32 max_wwt, max_rrt, max_wrt, max_rwt;
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u32 i;
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int wwt, rrt, wrt, rwt;
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int ext_wwt, ext_rrt, ext_wrt, ext_rwt;
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int max_wwt, max_rrt, max_wrt, max_rwt;
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for (i = 0; i < pstat_num; i++) {
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/* read wwt, rrt, wrt, rwt fields from timing_cfg_0 */
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if (!dram_timing->fsp_cfg_num) {
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tmp = ddrc_get_fsp_reg_setting(dram_timing->ddrc_cfg,
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dram_timing->ddrc_cfg_num,
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REG_DDR_TIMING_CFG_0);
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} else {
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tmp = ddrc_get_fsp_reg_setting(dram_timing->fsp_cfg[i].ddrc_cfg,
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ARRAY_SIZE(dram_timing->fsp_cfg[i].ddrc_cfg),
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REG_DDR_TIMING_CFG_0);
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}
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wwt = (tmp >> 24) & 0x3;
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rrt = (tmp >> 26) & 0x3;
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wrt = (tmp >> 28) & 0x3;
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rwt = (tmp >> 30) & 0x3;
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/* read wwt, rrt, wrt, rwt fields from timing_cfg_0 */
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tmp = readl(REG_DDR_TIMING_CFG_0);
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wwt = (tmp >> 24) & 0x3;
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rrt = (tmp >> 26) & 0x3;
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wrt = (tmp >> 28) & 0x3;
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rwt = (tmp >> 30) & 0x3;
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/* read rxt_wwt, ext_rrt, ext_wrt, ext_rwt fields from timing_cfg_4 */
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if (!dram_timing->fsp_cfg_num) {
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tmp_t = ddrc_get_fsp_reg_setting(dram_timing->ddrc_cfg,
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dram_timing->ddrc_cfg_num,
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REG_DDR_TIMING_CFG_4);
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} else {
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tmp_t = ddrc_get_fsp_reg_setting(dram_timing->fsp_cfg[i].ddrc_cfg,
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ARRAY_SIZE(dram_timing->fsp_cfg[i].ddrc_cfg),
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REG_DDR_TIMING_CFG_4);
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}
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ext_wwt = (tmp_t >> 8) & 0x3;
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ext_rrt = (tmp_t >> 10) & 0x3;
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ext_wrt = (tmp_t >> 12) & 0x3;
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ext_rwt = (tmp_t >> 14) & 0x3;
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/* read rxt_wwt, ext_rrt, ext_wrt, ext_rwt fields from timing_cfg_4 */
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tmp_t = readl(REG_DDR_TIMING_CFG_4);
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ext_wwt = (tmp >> 8) & 0x1;
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ext_rrt = (tmp >> 10) & 0x1;
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ext_wrt = (tmp >> 12) & 0x1;
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ext_rwt = (tmp >> 14) & 0x3;
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wwt = (ext_wwt << 2) | wwt;
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rrt = (ext_rrt << 2) | rrt;
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wrt = (ext_wrt << 2) | wrt;
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rwt = (ext_rwt << 2) | rwt;
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wwt = (ext_wwt << 2) | wwt;
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rrt = (ext_rrt << 2) | wwt;
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wrt = (ext_wrt << 2) | wrt;
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rwt = (ext_rwt << 2) | rwt;
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max_wwt = MAX(g_cdd_ww_max[0], wwt);
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max_rrt = MAX(g_cdd_rr_max[0], rrt);
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max_wrt = MAX(g_cdd_wr_max[0], wrt);
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max_rwt = MAX(g_cdd_rw_max[0], rwt);
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/* verify values to see if are bigger then 15 (4 bits) */
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if (max_wwt > 15)
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max_wwt = 15;
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if (max_rrt > 15)
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max_rrt = 15;
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if (max_wrt > 15)
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max_wrt = 15;
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if (max_rwt > 15)
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max_rwt = 15;
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/* calculate the maximum between controller and cdd values */
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max_wwt = MAX(g_cdd_ww_max[0], wwt);
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max_rrt = MAX(g_cdd_rr_max[0], rrt);
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max_wrt = MAX(g_cdd_wr_max[0], wrt);
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max_rwt = MAX(g_cdd_rw_max[0], rwt);
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/* recalculate timings for controller registers */
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wwt = max_wwt & 0x3;
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rrt = max_rrt & 0x3;
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wrt = max_wrt & 0x3;
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rwt = max_rwt & 0x3;
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/* verify values to see if are bigger then 7 or 15 (3 bits or 4 bits) */
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if (max_wwt > 7)
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max_wwt = 7;
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if (max_rrt > 7)
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max_rrt = 7;
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if (max_wrt > 7)
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max_wrt = 7;
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if (max_rwt > 15)
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max_rwt = 15;
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ext_wwt = (max_wwt & 0xC) >> 2;
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ext_rrt = (max_rrt & 0xC) >> 2;
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ext_wrt = (max_wrt & 0xC) >> 2;
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ext_rwt = (max_rwt & 0xC) >> 2;
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/* recalculate timings for controller registers */
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wwt = max_wwt & 0x3;
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rrt = max_rrt & 0x3;
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wrt = max_wrt & 0x3;
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rwt = max_rwt & 0x3;
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/* update timing_cfg_0 and timing_cfg_4 */
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tmp = (tmp & 0x00ffffff) | (rwt << 30) | (wrt << 28) |
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(rrt << 26) | (wwt << 24);
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tmp_t = (tmp_t & 0xFFFF00FF) | (ext_rwt << 14) |
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(ext_wrt << 12) | (ext_rrt << 10) | (ext_wwt << 8);
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ext_wwt = (max_wwt & 0x4) >> 2;
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ext_rrt = (max_rrt & 0x4) >> 2;
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ext_wrt = (max_wrt & 0x4) >> 2;
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ext_rwt = (max_rwt & 0xC) >> 2;
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/* update timing_cfg_0 and timing_cfg_4 */
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tmp = (tmp & 0x00ffffff) | (rwt << 30) | (wrt << 28) |
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(rrt << 26) | (wwt << 24);
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writel(tmp, REG_DDR_TIMING_CFG_0);
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tmp_t = (tmp_t & 0xFFFF2AFF) | (ext_rwt << 14) |
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(ext_wrt << 12) | (ext_rrt << 10) | (ext_wwt << 8);
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writel(tmp_t, REG_DDR_TIMING_CFG_4);
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if (!dram_timing->fsp_cfg_num) {
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ddrc_update_fsp_reg_setting(dram_timing->ddrc_cfg,
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dram_timing->ddrc_cfg_num,
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REG_DDR_TIMING_CFG_0, tmp);
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ddrc_update_fsp_reg_setting(dram_timing->ddrc_cfg,
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dram_timing->ddrc_cfg_num,
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REG_DDR_TIMING_CFG_4, tmp_t);
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} else {
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ddrc_update_fsp_reg_setting(dram_timing->fsp_cfg[i].ddrc_cfg,
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ARRAY_SIZE(dram_timing->fsp_cfg[i].ddrc_cfg),
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REG_DDR_TIMING_CFG_0, tmp);
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ddrc_update_fsp_reg_setting(dram_timing->fsp_cfg[i].ddrc_cfg,
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ARRAY_SIZE(dram_timing->fsp_cfg[i].ddrc_cfg),
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REG_DDR_TIMING_CFG_4, tmp_t);
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}
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}
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}
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u32 ddrc_mrr(u32 chip_select, u32 mode_reg_num, u32 *mode_reg_val)
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@ -313,13 +367,13 @@ int ddr_init(struct dram_timing_info *dram_timing)
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debug("DDRINFO: ddrphy config done\n");
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update_umctl2_rank_space_setting(dram_timing, dram_timing->fsp_msg_num - 1);
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/* rogram the ddrc registers */
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debug("DDRINFO: ddrc config start\n");
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ddrc_config(dram_timing);
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debug("DDRINFO: ddrc config done\n");
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update_umctl2_rank_space_setting(dram_timing->fsp_msg_num - 1);
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#ifdef CONFIG_IMX9_DRAM_PM_COUNTER
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writel(0x200000, REG_DDR_DEBUG_19);
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#endif
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