Merge https://source.denx.de/u-boot/custodians/u-boot-riscv

arch/riscv/Kconfig

@@ -179,6 +179,11 @@ config SPL_SIFIVE_CLINT
 	  The SiFive CLINT block holds memory-mapped control and status registers
 	  associated with software and timer interrupts.
 
+config SIFIVE_CACHE
+	bool
+	help
+	  This enables the operations to configure SiFive cache
+
 config ANDES_PLIC
 	bool
 	depends on RISCV_MMODE || SPL_RISCV_MMODE

arch/riscv/cpu/fu540/Kconfig

@@ -19,6 +19,8 @@ config SIFIVE_FU540
 	imply SMP
 	imply CLK_SIFIVE
 	imply CLK_SIFIVE_PRCI
+	imply SIFIVE_CACHE
+	imply SIFIVE_CCACHE
 	imply SIFIVE_SERIAL
 	imply MACB
 	imply MII

arch/riscv/cpu/fu540/Makefile

@@ -8,5 +8,4 @@ obj-y += spl.o
 else
 obj-y += dram.o
 obj-y += cpu.o
-obj-y += cache.o
 endif

arch/riscv/cpu/fu540/cache.c

@@ -1,55 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2020 SiFive, Inc
- *
- * Authors:
- *   Pragnesh Patel <pragnesh.patel@sifive.com>
- */
-
-#include <common.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <linux/bitops.h>
-
-/* Register offsets */
-#define L2_CACHE_CONFIG	0x000
-#define L2_CACHE_ENABLE	0x008
-
-#define MASK_NUM_WAYS	GENMASK(15, 8)
-#define NUM_WAYS_SHIFT	8
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int cache_enable_ways(void)
-{
-	const void *blob = gd->fdt_blob;
-	int node;
-	fdt_addr_t base;
-	u32 config;
-	u32 ways;
-
-	volatile u32 *enable;
-
-	node = fdt_node_offset_by_compatible(blob, -1,
-					     "sifive,fu540-c000-ccache");
-
-	if (node < 0)
-		return node;
-
-	base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
-						NULL, false);
-	if (base == FDT_ADDR_T_NONE)
-		return FDT_ADDR_T_NONE;
-
-	config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
-	ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
-
-	enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
-
-	/* memory barrier */
-	mb();
-	(*enable) = ways - 1;
-	/* memory barrier */
-	mb();
-	return 0;
-}

arch/riscv/cpu/fu740/Kconfig

@@ -19,6 +19,8 @@ config SIFIVE_FU740
 	imply SMP
 	imply CLK_SIFIVE
 	imply CLK_SIFIVE_PRCI
+	imply SIFIVE_CACHE
+	imply SIFIVE_CCACHE
 	imply SIFIVE_SERIAL
 	imply MACB
 	imply MII

arch/riscv/cpu/fu740/Makefile

@@ -8,5 +8,4 @@ obj-y += spl.o
 else
 obj-y += dram.o
 obj-y += cpu.o
-obj-y += cache.o
 endif

arch/riscv/cpu/fu740/cache.c

@@ -1,55 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2020-2021 SiFive, Inc
- *
- * Authors:
- *   Pragnesh Patel <pragnesh.patel@sifive.com>
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <linux/bitops.h>
-#include <asm/global_data.h>
-
-/* Register offsets */
-#define L2_CACHE_CONFIG	0x000
-#define L2_CACHE_ENABLE	0x008
-
-#define MASK_NUM_WAYS	GENMASK(15, 8)
-#define NUM_WAYS_SHIFT	8
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int cache_enable_ways(void)
-{
-	const void *blob = gd->fdt_blob;
-	int node;
-	fdt_addr_t base;
-	u32 config;
-	u32 ways;
-
-	volatile u32 *enable;
-
-	node = fdt_node_offset_by_compatible(blob, -1,
-					     "sifive,fu740-c000-ccache");
-
-	if (node < 0)
-		return node;
-
-	base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
-						NULL, false);
-	if (base == FDT_ADDR_T_NONE)
-		return FDT_ADDR_T_NONE;
-
-	config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
-	ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
-
-	enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
-
-	/* memory barrier */
-	mb();
-	(*enable) = ways - 1;
-	/* memory barrier */
-	mb();
-	return 0;
-}

arch/riscv/include/asm/arch-fu540/cache.h

@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2020 SiFive, Inc.
- *
- * Authors:
- *   Pragnesh Patel <pragnesh.patel@sifve.com>
- */
-
-#ifndef _CACHE_SIFIVE_H
-#define _CACHE_SIFIVE_H
-
-int cache_enable_ways(void);
-
-#endif /* _CACHE_SIFIVE_H */

arch/riscv/include/asm/arch-fu740/cache.h

@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2020-2021 SiFive, Inc.
- *
- * Authors:
- *   Pragnesh Patel <pragnesh.patel@sifve.com>
- */
-
-#ifndef _CACHE_SIFIVE_H
-#define _CACHE_SIFIVE_H
-
-int cache_enable_ways(void);
-
-#endif /* _CACHE_SIFIVE_H */

arch/riscv/include/asm/cache.h

@@ -8,7 +8,7 @@
 #define _ASM_RISCV_CACHE_H
 
 /* cache */
-void	cache_flush(void);
+void cache_flush(void);
 
 /*
  * The current upper bound for RISCV L1 data cache line sizes is 32 bytes.

arch/riscv/lib/Makefile

@@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
 obj-$(CONFIG_CMD_GO) += boot.o
 obj-y	+= cache.o
+obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
 ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
 obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
 obj-$(CONFIG_ANDES_PLIC) += andes_plic.o

arch/riscv/lib/cache.c

@@ -70,3 +70,7 @@ __weak int dcache_status(void)
 {
 	return 0;
 }
+
+__weak void enable_caches(void)
+{
+}

arch/riscv/lib/interrupts.c

@@ -51,6 +51,38 @@ static void show_regs(struct pt_regs *regs)
 #endif
 }
 
+/**
+ * instr_len() - get instruction length
+ *
+ * @i:		low 16 bits of the instruction
+ * Return:	number of u16 in instruction
+ */
+static int instr_len(u16 i)
+{
+	if ((i & 0x03) != 0x03)
+		return 1;
+	/* Instructions with more than 32 bits are not yet specified */
+	return 2;
+}
+
+/**
+ * show_code() - display code leading to exception
+ *
+ * @epc:	program counter
+ */
+static void show_code(ulong epc)
+{
+	u16 *pos = (u16 *)(epc & ~1UL);
+	int i, len = instr_len(*pos);
+
+	printf("\nCode: ");
+	for (i = -8; i; ++i)
+		printf("%04x ", pos[i]);
+	printf("(");
+	for (i = 0; i < len; ++i)
+		printf("%04x%s", pos[i], i + 1 == len ? ")\n" : " ");
+}
+
 static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs)
 {
 	static const char * const exception_code[] = {
@@ -85,6 +117,7 @@ static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs)
 		       epc - gd->reloc_off, regs->ra - gd->reloc_off);
 
 	show_regs(regs);
+	show_code(epc);
 	show_efi_loaded_images(epc);
 	panic("\n");
 }

arch/riscv/lib/sifive_cache.c

@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 SiFive, Inc
+ */
+
+#include <common.h>
+#include <cache.h>
+#include <cpu_func.h>
+#include <dm.h>
+
+void enable_caches(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	/* Enable ways of ccache */
+	ret = uclass_get_device_by_driver(UCLASS_CACHE,
+					  DM_DRIVER_GET(sifive_ccache),
+					  &dev);
+	if (ret) {
+		log_debug("Cannot enable cache ways");
+	} else {
+		ret = cache_enable(dev);
+		if (ret)
+			log_debug("ccache enable failed");
+	}
+}

board/sifive/unleashed/unleashed.c

@@ -6,6 +6,7 @@
  *   Anup Patel <anup.patel@wdc.com>
  */
 
+#include <cpu_func.h>
 #include <dm.h>
 #include <env.h>
 #include <init.h>
@@ -15,7 +16,6 @@
 #include <linux/delay.h>
 #include <misc.h>
 #include <spl.h>
-#include <asm/arch/cache.h>
 #include <asm/sections.h>
 
 /*
@@ -126,14 +126,8 @@ void *board_fdt_blob_setup(void)
 
 int board_init(void)
 {
-	int ret;
-
 	/* enable all cache ways */
-	ret = cache_enable_ways();
-	if (ret) {
-		debug("%s: could not enable cache ways\n", __func__);
-		return ret;
-	}
+	enable_caches();
 
 	return 0;
 }

board/sifive/unmatched/unmatched.c

@@ -7,8 +7,8 @@
  */
 
 #include <common.h>
+#include <cpu_func.h>
 #include <dm.h>
-#include <asm/arch/cache.h>
 #include <asm/sections.h>
 
 void *board_fdt_blob_setup(void)
@@ -23,13 +23,8 @@ void *board_fdt_blob_setup(void)
 
 int board_init(void)
 {
-	int ret;
-
 	/* enable all cache ways */
-	ret = cache_enable_ways();
-	if (ret) {
-		debug("%s: could not enable cache ways\n", __func__);
-		return ret;
-	}
+	enable_caches();
+
 	return 0;
 }

common/board_r.c

@@ -114,7 +114,7 @@ static int initr_reloc(void)
 	return 0;
 }
 
-#ifdef CONFIG_ARM
+#if defined(CONFIG_ARM) || defined(CONFIG_RISCV)
 /*
  * Some of these functions are needed purely because the functions they
  * call return void. If we change them to return 0, these stubs can go away.
@@ -607,7 +607,7 @@ static init_fnc_t init_sequence_r[] = {
 	initr_trace,
 	initr_reloc,
 	/* TODO: could x86/PPC have this also perhaps? */
-#ifdef CONFIG_ARM
+#if defined(CONFIG_ARM) || defined(CONFIG_RISCV)
 	initr_caches,
 	/* Note: For Freescale LS2 SoCs, new MMU table is created in DDR.
 	 *	 A temporary mapping of IFC high region is since removed,

configs/qemu-riscv32_spl_defconfig

@@ -10,6 +10,7 @@ CONFIG_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
 CONFIG_DISPLAY_CPUINFO=y
 CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_CMD_SBI=y
 # CONFIG_CMD_MII is not set
 CONFIG_OF_PRIOR_STAGE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y

configs/qemu-riscv64_spl_defconfig

@@ -11,6 +11,7 @@ CONFIG_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
 CONFIG_DISPLAY_CPUINFO=y
 CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_CMD_SBI=y
 # CONFIG_CMD_MII is not set
 CONFIG_OF_PRIOR_STAGE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y

configs/sifive_unmatched_defconfig

@@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="hifive-unmatched-a00"
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_AHCI=y
 CONFIG_TARGET_SIFIVE_UNMATCHED=y
 CONFIG_ARCH_RV64I=y
 CONFIG_RISCV_SMODE=y
@@ -28,12 +29,16 @@ CONFIG_CMD_GPT_RENAME=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
 CONFIG_SPL_CLK=y
 CONFIG_E1000=y
 CONFIG_NVME=y
 CONFIG_PCI=y
 CONFIG_PCIE_DW_SIFIVE=y
 CONFIG_DM_RESET=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_PCI=y

drivers/cache/Kconfig

@@ -39,4 +39,11 @@ config NCORE_CACHE
 	  controller. The driver initializes cache directories and coherent
 	  agent interfaces.
 
+config SIFIVE_CCACHE
+	bool "SiFive composable cache"
+	select CACHE
+	help
+	  This driver is for SiFive Composable L2/L3 cache. It enables cache
+	  ways of composable cache.
+
 endmenu

drivers/cache/Makefile

@@ -4,3 +4,4 @@ obj-$(CONFIG_SANDBOX) += sandbox_cache.o
 obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
 obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o
 obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
+obj-$(CONFIG_SIFIVE_CCACHE) += cache-sifive-ccache.o

drivers/cache/cache-sifive-ccache.c

@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 SiFive
+ */
+
+#include <common.h>
+#include <cache.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <dm/device.h>
+#include <linux/bitfield.h>
+
+#define SIFIVE_CCACHE_CONFIG		0x000
+#define SIFIVE_CCACHE_CONFIG_WAYS	GENMASK(15, 8)
+
+#define SIFIVE_CCACHE_WAY_ENABLE	0x008
+
+struct sifive_ccache {
+	void __iomem *base;
+};
+
+static int sifive_ccache_enable(struct udevice *dev)
+{
+	struct sifive_ccache *priv = dev_get_priv(dev);
+	u32 config;
+	u32 ways;
+
+	/* Enable all ways of composable cache */
+	config = readl(priv->base + SIFIVE_CCACHE_CONFIG);
+	ways = FIELD_GET(SIFIVE_CCACHE_CONFIG_WAYS, config);
+
+	writel(ways - 1, priv->base + SIFIVE_CCACHE_WAY_ENABLE);
+
+	return 0;
+}
+
+static int sifive_ccache_get_info(struct udevice *dev, struct cache_info *info)
+{
+	struct sifive_ccache *priv = dev_get_priv(dev);
+
+	info->base = (phys_addr_t)priv->base;
+
+	return 0;
+}
+
+static const struct cache_ops sifive_ccache_ops = {
+	.enable = sifive_ccache_enable,
+	.get_info = sifive_ccache_get_info,
+};
+
+static int sifive_ccache_probe(struct udevice *dev)
+{
+	struct sifive_ccache *priv = dev_get_priv(dev);
+
+	priv->base = dev_read_addr_ptr(dev);
+	if (!priv->base)
+		return -EINVAL;
+
+	return 0;
+}
+
+static const struct udevice_id sifive_ccache_ids[] = {
+	{ .compatible = "sifive,fu540-c000-ccache" },
+	{ .compatible = "sifive,fu740-c000-ccache" },
+	{}
+};
+
+U_BOOT_DRIVER(sifive_ccache) = {
+	.name = "sifive_ccache",
+	.id = UCLASS_CACHE,
+	.of_match = sifive_ccache_ids,
+	.probe = sifive_ccache_probe,
+	.priv_auto = sizeof(struct sifive_ccache),
+	.ops = &sifive_ccache_ops,
+};

drivers/i2c/ocores_i2c.c

@@ -626,6 +626,7 @@ static const struct udevice_id ocores_i2c_ids[] = {
 { .compatible = "aeroflexgaisler,i2cmst", .data = TYPE_GRLIB },
 { .compatible = "sifive,fu540-c000-i2c" },
 { .compatible = "sifive,i2c0" },
+{ }
 };
 
 U_BOOT_DRIVER(i2c_ocores) = {

include/configs/sifive-unmatched.h

@@ -40,6 +40,8 @@
 
 #define CONFIG_SYS_CACHELINE_SIZE	64
 
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
+
 /* Environment options */
 
 #ifndef CONFIG_SPL_BUILD
@@ -47,6 +49,7 @@
 	func(NVME, nvme, 0) \
 	func(USB, usb, 0) \
 	func(MMC, mmc, 0) \
+	func(SCSI, scsi, 0) \
 	func(PXE, pxe, na) \
 	func(DHCP, dhcp, na)