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Merge branch 'master' of git://git.denx.de/u-boot-mips

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This commit is contained in:
Tom Rini 2013-12-02 08:44:28 -05:00
commit 19210ae983
4 changed files with 25 additions and 3 deletions
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7
arch/mips/include/asm/malta.h
View file

@ -56,5 +56,12 @@
#define PCI_CFG_PIIX4_PIRQRCB 0x61
#define PCI_CFG_PIIX4_PIRQRCC 0x62
#define PCI_CFG_PIIX4_PIRQRCD 0x63
#define PCI_CFG_PIIX4_SERIRQC 0x64
#define PCI_CFG_PIIX4_GENCFG 0xb0
#define PCI_CFG_PIIX4_SERIRQC_EN (1 << 7)
#define PCI_CFG_PIIX4_SERIRQC_CONT (1 << 6)
#define PCI_CFG_PIIX4_GENCFG_SERIRQ (1 << 16)
#endif /* _MIPS_ASM_MALTA_H */

6
arch/mips/lib/bootm.c
View file

@ -196,8 +196,10 @@ static void boot_prep_linux(bootm_headers_t *images)
if (cp)
linux_env_set("eth1addr", cp);
if (mips_boot_malta)
linux_env_set("modetty0", "38400n8r");
if (mips_boot_malta) {
sprintf(env_buf, "%un8r", gd->baudrate);
linux_env_set("modetty0", env_buf);
}
}
static void boot_jump_linux(bootm_headers_t *images)

12
board/imgtec/malta/malta.c
View file

@ -171,6 +171,8 @@ struct serial_device *default_serial_console(void)
void pci_init_board(void)
{
pci_dev_t bdf;
u32 val32;
u8 val8;
switch (malta_sys_con()) {
case SYSCON_GT64120:
@ -205,4 +207,14 @@ void pci_init_board(void)
pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10);
pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11);
pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11);
/* mux SERIRQ onto SERIRQ pin */
pci_read_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, &val32);
val32 |= PCI_CFG_PIIX4_GENCFG_SERIRQ;
pci_write_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, val32);
/* enable SERIRQ - Linux currently depends upon this */
pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8);
val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT;
pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8);
}

3
include/configs/malta.h
View file

@ -54,6 +54,7 @@
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024)
/*
* Console configuration
@ -80,7 +81,7 @@
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK 115200
#define CONFIG_SYS_NS16550_CLK (115200 * 16)
#define CONFIG_SYS_NS16550_COM1 CKSEG1ADDR(MALTA_GT_UART0_BASE)
#define CONFIG_SYS_NS16550_COM2 CKSEG1ADDR(MALTA_MSC01_UART0_BASE)
#define CONFIG_CONS_INDEX 1