- Bug fixes related to FSL-IFC, watchdog - layerscape-pcie, flexspi, T2080rdb.
This commit is contained in:
commit
1886e9d0c3
23 changed files with 45 additions and 35 deletions
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@ -30,3 +30,11 @@
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spi-max-frequency = <10000000>; /* input clock */
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};
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};
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&i2c0 {
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status = "okay";
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rtc@68 {
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compatible = "dallas,ds1339";
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reg = <0x68>;
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};
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};
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@ -34,6 +34,11 @@ T2080 includes the following functions and features:
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- Support for hardware virtualization and partitioning enforcement
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- QorIQ Platform's Trust Architecture 2.0
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User Guide
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----------
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The T2080RDB User Guide is available on the web at
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https://www.nxp.com/docs/en/user-guide/T2080RDBPCUG.pdf
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Differences between T2080 and T2081
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-----------------------------------
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Feature T2080 T2081
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@ -77,6 +77,8 @@ CONFIG_DM_PCI=y
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CONFIG_DM_PCI_COMPAT=y
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CONFIG_PCIE_FSL=y
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CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
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CONFIG_DM_RTC=y
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CONFIG_RTC_DS1307=y
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CONFIG_SYS_NS16550=y
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CONFIG_SPI=y
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CONFIG_DM_SPI=y
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@ -74,6 +74,8 @@ CONFIG_DM_PCI=y
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CONFIG_DM_PCI_COMPAT=y
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CONFIG_PCIE_FSL=y
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CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
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CONFIG_DM_RTC=y
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CONFIG_RTC_DS1307=y
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CONFIG_SYS_NS16550=y
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CONFIG_SPI=y
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CONFIG_DM_SPI=y
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@ -76,6 +76,8 @@ CONFIG_DM_PCI=y
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CONFIG_DM_PCI_COMPAT=y
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CONFIG_PCIE_FSL=y
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CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
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CONFIG_DM_RTC=y
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CONFIG_RTC_DS1307=y
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CONFIG_SYS_NS16550=y
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CONFIG_SPI=y
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CONFIG_DM_SPI=y
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@ -61,6 +61,8 @@ CONFIG_DM_PCI=y
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CONFIG_DM_PCI_COMPAT=y
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CONFIG_PCIE_FSL=y
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CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
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CONFIG_DM_RTC=y
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CONFIG_RTC_DS1307=y
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CONFIG_SYS_NS16550=y
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CONFIG_SPI=y
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CONFIG_DM_SPI=y
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@ -49,8 +49,9 @@ CONFIG_DM_MMC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_MTD=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_EON=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_SST=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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CONFIG_PHYLIB=y
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CONFIG_PHY_AQUANTIA=y
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@ -8,7 +8,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000
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CONFIG_SYS_MEMTEST_END=0x9fffffff
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CONFIG_ENV_SIZE=0x2000
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CONFIG_ENV_OFFSET=0x500000
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CONFIG_ENV_SECT_SIZE=0x40000
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CONFIG_ENV_SECT_SIZE=0x20000
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CONFIG_DM_GPIO=y
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CONFIG_FSPI_AHB_EN_4BYTE=y
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CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
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@ -55,8 +55,9 @@ CONFIG_DM_MMC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_MTD=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_EON=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_SST=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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CONFIG_PHYLIB=y
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CONFIG_PHY_AQUANTIA=y
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@ -7,7 +7,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000
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CONFIG_SYS_MEMTEST_END=0x9fffffff
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CONFIG_ENV_SIZE=0x2000
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CONFIG_ENV_OFFSET=0x500000
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CONFIG_ENV_SECT_SIZE=0x40000
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CONFIG_ENV_SECT_SIZE=0x20000
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CONFIG_DM_GPIO=y
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CONFIG_FSPI_AHB_EN_4BYTE=y
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CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
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@ -55,8 +55,9 @@ CONFIG_DM_MMC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_MTD=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_EON=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_SST=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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CONFIG_PHYLIB=y
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CONFIG_PHY_AQUANTIA=y
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@ -48,7 +48,6 @@ CONFIG_DM_MMC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_MTD=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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CONFIG_PHYLIB=y
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@ -8,7 +8,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000
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CONFIG_SYS_MEMTEST_END=0x9fffffff
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CONFIG_ENV_SIZE=0x2000
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CONFIG_ENV_OFFSET=0x500000
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CONFIG_ENV_SECT_SIZE=0x40000
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CONFIG_ENV_SECT_SIZE=0x20000
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CONFIG_DM_GPIO=y
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CONFIG_FSPI_AHB_EN_4BYTE=y
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CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
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@ -54,7 +54,6 @@ CONFIG_DM_MMC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_MTD=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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CONFIG_PHYLIB=y
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@ -50,7 +50,6 @@ CONFIG_FSL_ESDHC=y
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CONFIG_MTD=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH_EON=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_SST=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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@ -57,7 +57,6 @@ CONFIG_FSL_ESDHC=y
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CONFIG_MTD=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH_EON=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_SST=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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@ -46,7 +46,6 @@ CONFIG_MMC_HS400_SUPPORT=y
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CONFIG_FSL_ESDHC=y
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CONFIG_MTD=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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CONFIG_PHYLIB=y
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@ -55,7 +55,6 @@ CONFIG_MMC_HS400_SUPPORT=y
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CONFIG_FSL_ESDHC=y
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CONFIG_MTD=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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CONFIG_PHYLIB=y
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@ -55,7 +55,6 @@ CONFIG_MMC_HS400_SUPPORT=y
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CONFIG_FSL_ESDHC=y
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CONFIG_MTD=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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CONFIG_PHYLIB=y
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@ -411,9 +411,16 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
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/* READID must read all possible bytes while CEB is active */
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case NAND_CMD_READID:
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case NAND_CMD_PARAM: {
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/*
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* For READID, read 8 bytes that are currently used.
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* For PARAM, read all 3 copies of 256-bytes pages.
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*/
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int len = 8;
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int timing = IFC_FIR_OP_RB;
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if (command == NAND_CMD_PARAM)
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if (command == NAND_CMD_PARAM) {
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timing = IFC_FIR_OP_RBCD;
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len = 256 * 3;
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}
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ifc_out32(&ifc->ifc_nand.nand_fir0,
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(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
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command << IFC_NAND_FCR0_CMD0_SHIFT);
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ifc_out32(&ifc->ifc_nand.row3, column);
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/*
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* although currently it's 8 bytes for READID, we always read
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* the maximum 256 bytes(for PARAM)
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*/
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ifc_out32(&ifc->ifc_nand.nand_fbcr, 256);
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ctrl->read_bytes = 256;
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ifc_out32(&ifc->ifc_nand.nand_fbcr, len);
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ctrl->read_bytes = len;
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set_addr(mtd, 0, 0, 0);
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fsl_ifc_run_command(mtd);
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@ -244,7 +244,7 @@ static int ls_pcie_ep_probe(struct udevice *dev)
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int ret;
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u32 svr;
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pcie = devm_kmalloc(dev, sizeof(*pcie), GFP_KERNEL);
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pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
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if (!pcie)
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return -ENOMEM;
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@ -254,7 +254,7 @@ static int ls_pcie_probe(struct udevice *dev)
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pcie_rc->bus = dev;
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pcie = devm_kmalloc(dev, sizeof(*pcie), GFP_KERNEL);
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pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
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if (!pcie)
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return -ENOMEM;
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@ -23,6 +23,7 @@
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enum ds_type {
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ds_1307,
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ds_1337,
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ds_1339,
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ds_1340,
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m41t11,
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mcp794xx,
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@ -344,6 +345,7 @@ static const struct rtc_ops ds1307_rtc_ops = {
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static const struct udevice_id ds1307_rtc_ids[] = {
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{ .compatible = "dallas,ds1307", .data = ds_1307 },
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{ .compatible = "dallas,ds1337", .data = ds_1337 },
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{ .compatible = "dallas,ds1339", .data = ds_1339 },
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{ .compatible = "dallas,ds1340", .data = ds_1340 },
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{ .compatible = "microchip,mcp7941x", .data = mcp794xx },
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{ .compatible = "st,m41t11", .data = m41t11 },
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@ -81,12 +81,6 @@
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#define CONFIG_SYS_SCSI_MAX_LUN 1
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#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
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CONFIG_SYS_SCSI_MAX_LUN)
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/* DSPI */
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#ifdef CONFIG_FSL_DSPI
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#define CONFIG_SPI_FLASH_SST
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#define CONFIG_SPI_FLASH_EON
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#endif
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#ifndef SPL_NO_ENV
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#undef CONFIG_EXTRA_ENV_SETTINGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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@ -154,12 +154,6 @@
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#endif
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#endif
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/* FlexSPI */
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#ifdef CONFIG_NXP_FSPI
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#define NXP_FSPI_FLASH_SIZE SZ_64M
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#define NXP_FSPI_FLASH_NUM 1
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#endif
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/* GPIO */
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#ifdef CONFIG_DM_GPIO
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#ifndef CONFIG_MPC8XXX_GPIO
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@ -140,7 +140,7 @@
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#define CSOR_NOR_ADM_SHIFT_SHIFT 13
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#define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
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/* Type of the NOR device hooked */
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#define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000
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#define CSOR_NOR_NOR_MODE_ASYNC_NOR 0x00000000
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#define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020
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/* Time for Read Enable High to Output High Impedance */
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#define CSOR_NOR_TRHZ_MASK 0x0000001C
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