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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

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This commit is contained in:
Wolfgang Denk 2011-04-10 21:24:40 +02:00
commit 17e967b3df
23 changed files with 393 additions and 158 deletions
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11
arch/powerpc/cpu/mpc85xx/cpu.c
View file

@ -299,6 +299,16 @@ void mpc85xx_reginfo(void)
/* Common ddr init for non-corenet fsl 85xx platforms */
#ifndef CONFIG_FSL_CORENET
#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_INIT_L2_ADDR)
phys_size_t initdram(int board_type)
{
#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
return fsl_ddr_sdram_size();
#else
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
#endif
}
#else /* CONFIG_SYS_RAMBOOT */
phys_size_t initdram(int board_type)
{
phys_size_t dram_size = 0;
@ -348,6 +358,7 @@ phys_size_t initdram(int board_type)
puts("DDR: ");
return dram_size;
}
#endif /* CONFIG_SYS_RAMBOOT */
#endif
#if CONFIG_POST & CONFIG_SYS_POST_MEMORY

19
arch/powerpc/cpu/mpc85xx/cpu_init.c
View file

@ -145,6 +145,22 @@ static void enable_cpc(void)
for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
u32 cpccfg0 = in_be32(&cpc->cpccfg0);
size += CPC_CFG0_SZ_K(cpccfg0);
#ifdef CONFIG_RAMBOOT_PBL
if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
/* find and disable LAW of SRAM */
struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
if (law.index == -1) {
printf("\nFatal error happened\n");
return;
}
disable_law(law.index);
clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
out_be32(&cpc->cpccsr0, 0);
out_be32(&cpc->cpcsrcr0, 0);
}
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
@ -168,6 +184,9 @@ void invalidate_cpc(void)
cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
/* skip CPC when it used as all SRAM */
if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
continue;
/* Flash invalidate the CPC and clear all the locks */
out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))

15
arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
View file

@ -33,17 +33,15 @@ void cpu_init_f(void)
*/
out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8);
#if defined(CONFIG_NAND_BR_PRELIM) && defined(CONFIG_NAND_OR_PRELIM)
set_lbc_br(0, CONFIG_NAND_BR_PRELIM);
set_lbc_or(0, CONFIG_NAND_OR_PRELIM);
#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
#else
#error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined
#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM must be defined
#endif
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
char *l2srbar;
int i;
out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
@ -54,10 +52,5 @@ void cpu_init_f(void)
/* set L2E=1 & L2SRAM=001 */
out_be32(&l2cache->l2ctl,
(MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
/* Initialize L2 SRAM to zero */
l2srbar = (char *)CONFIG_SYS_INIT_L2_ADDR;
for (i = 0; i < CONFIG_SYS_L2_SIZE; i++)
l2srbar[i] = 0;
#endif
}

106
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
View file

@ -109,10 +109,13 @@ int serdes_lane_enabled(int lane)
return 0;
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
if (!IS_SVR_REV(get_svr(), 1, 0))
if (bank > 0)
return !(srds_lpd_b[bank] &
(8 >> (lane - (6 + 4 * bank))));
/*
* For banks two and three, use the srds_lpd_b[] array instead of the
* RCW, because this array contains the real values of SRDS_LPD_B2 and
* SRDS_LPD_B3.
*/
if (bank > 0)
return !(srds_lpd_b[bank] & (8 >> (lane - (6 + 4 * bank))));
#endif
return !(in_be32(&gur->rcwsr[word]) & (0x80000000 >> bit));
@ -303,15 +306,19 @@ void fsl_serdes_init(void)
}
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
if (!IS_SVR_REV(get_svr(), 1, 0))
for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) {
sprintf(srds_lpd_opt, "fsl_srds_lpd_b%u", bank + 1);
srds_lpd_arg = hwconfig_subarg_f("serdes", srds_lpd_opt,
&arglen, buf);
if (srds_lpd_arg)
srds_lpd_b[bank] = simple_strtoul(srds_lpd_arg,
NULL, 0);
}
/*
* Store the values of the fsl_srds_lpd_b2 and fsl_srds_lpd_b3
* hwconfig options into the srds_lpd_b[] array. See README.p4080ds
* for a description of these options.
*/
for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) {
sprintf(srds_lpd_opt, "fsl_srds_lpd_b%u", bank + 1);
srds_lpd_arg =
hwconfig_subarg_f("serdes", srds_lpd_opt, &arglen, buf);
if (srds_lpd_arg)
srds_lpd_b[bank] =
simple_strtoul(srds_lpd_arg, NULL, 0) & 0xf;
}
#endif
/* Look for banks with all lanes disabled, and power down the bank. */
@ -324,32 +331,12 @@ void fsl_serdes_init(void)
}
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
if (IS_SVR_REV(get_svr(), 1, 0)) {
/* At least one bank must be disabled due to SERDES8. If
* no bank is found to be disabled based on lane
* disables, disable bank 3 because we can't turn off its
* lanes in the RCW without disabling MDIO due to erratum
* GEN8.
*
* This means that if you are relying on bank 3 being
* disabled to avoid SERDES8, in some cases you cannot
* also disable all lanes of another bank, or else bank
* 3 won't be disabled, leaving you with a configuration
* that isn't valid according to SERDES8 (e.g. if banks
* 2 and 3 have the same clock, and bank 1 is disabled
* instead of 3).
*/
for (bank = 0; bank < SRDS_MAX_BANK; bank++) {
if (!have_bank[bank])
break;
}
if (bank == SRDS_MAX_BANK)
have_bank[FSL_SRDS_BANK_3] = 0;
} else {
if (have_bank[FSL_SRDS_BANK_2])
have_bank[FSL_SRDS_BANK_3] = 1;
}
/*
* Bank two uses the clock from bank three, so if bank two is enabled,
* then bank three must also be enabled.
*/
if (have_bank[FSL_SRDS_BANK_2])
have_bank[FSL_SRDS_BANK_3] = 1;
#endif
for (bank = 0; bank < SRDS_MAX_BANK; bank++) {
@ -455,19 +442,16 @@ void fsl_serdes_init(void)
bank = idx;
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
if (!IS_SVR_REV(get_svr(), 1, 0)) {
/*
* Change bank init order to 0, 2, 1, so that the
* third bank's PLL is established before we
* start the second bank which shares the third
* bank's PLL.
*/
/*
* Change bank init order to 0, 2, 1, so that the third bank's
* PLL is established before we start the second bank. The
* second bank uses the third bank's PLL.
*/
if (idx == 1)
bank = FSL_SRDS_BANK_3;
else if (idx == 2)
bank = FSL_SRDS_BANK_2;
}
if (idx == 1)
bank = FSL_SRDS_BANK_3;
else if (idx == 2)
bank = FSL_SRDS_BANK_2;
#endif
/* Skip disabled banks */
@ -475,14 +459,18 @@ void fsl_serdes_init(void)
continue;
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
if (!IS_SVR_REV(get_svr(), 1, 0)) {
if (idx == 1) {
p4080_erratum_serdes8(srds_regs, gur,
serdes8_devdisr,
serdes8_devdisr2, cfg);
} else if (idx == 2) {
enable_bank(gur, FSL_SRDS_BANK_2);
}
if (idx == 1) {
/*
* Re-enable devices on banks two and three that were
* disabled by the RCW, and then enable bank three. The
* devices need to be enabled before either bank is
* powered up.
*/
p4080_erratum_serdes8(srds_regs, gur, serdes8_devdisr,
serdes8_devdisr2, cfg);
} else if (idx == 2) {
/* Eable bank two now that bank three is enabled. */
enable_bank(gur, FSL_SRDS_BANK_2);
}
#endif

8
arch/powerpc/cpu/mpc85xx/speed.c
View file

@ -28,6 +28,7 @@
#include <common.h>
#include <ppc_asm.tmpl>
#include <linux/compiler.h>
#include <asm/processor.h>
#include <asm/io.h>
@ -156,7 +157,7 @@ void get_sys_info (sys_info_t * sysInfo)
#endif
int i;
#ifdef CONFIG_QE
u32 qe_ratio;
__maybe_unused u32 qe_ratio;
#endif
plat_ratio = (gur->porpllsr) & 0x0000003e;
@ -184,10 +185,15 @@ void get_sys_info (sys_info_t * sysInfo)
#endif
#ifdef CONFIG_QE
#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
defined(CONFIG_P1021) || defined(CONFIG_P1025)
sysInfo->freqQE = sysInfo->freqSystemBus;
#else
qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
#endif
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
sysInfo->freqFMan[0] = sysInfo->freqSystemBus;

14
arch/powerpc/include/asm/config_mpc85xx.h
View file

@ -88,6 +88,7 @@
#elif defined(CONFIG_P1010)
#define CONFIG_MAX_CPUS 1
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
@ -115,6 +116,9 @@
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
/* P1013 is single core version of P1022 */
#elif defined(CONFIG_P1013)
@ -128,6 +132,7 @@
#elif defined(CONFIG_P1014)
#define CONFIG_MAX_CPUS 1
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
@ -155,6 +160,9 @@
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
/* P1017 is single core version of P1023 */
#elif defined(CONFIG_P1017)
@ -185,6 +193,9 @@
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_P1022)
#define CONFIG_MAX_CPUS 2
@ -225,6 +236,9 @@
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
/* P2010 is single core version of P2020 */
#elif defined(CONFIG_P2010)

1
arch/powerpc/include/asm/fsl_ddr_sdram.h
View file

@ -271,6 +271,7 @@ typedef struct memctl_options_s {
} memctl_options_t;
extern phys_size_t fsl_ddr_sdram(void);
extern phys_size_t fsl_ddr_sdram_size(void);
extern int fsl_use_spd(void);
extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num);

53
arch/powerpc/include/asm/immap_85xx.h
View file

@ -1923,7 +1923,31 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR_SD_DATA 0x80000000
#define MPC85xx_PMUXCR_SDHC_CD 0x40000000
#define MPC85xx_PMUXCR_SDHC_WP 0x20000000
#define MPC85xx_PMUXCR_TDM_ENA 0x00800000
#define MPC85xx_PMUXCR_QE0 0x00008000
#define MPC85xx_PMUXCR_QE1 0x00004000
#define MPC85xx_PMUXCR_QE2 0x00002000
#define MPC85xx_PMUXCR_QE3 0x00001000
#define MPC85xx_PMUXCR_QE4 0x00000800
#define MPC85xx_PMUXCR_QE5 0x00000400
#define MPC85xx_PMUXCR_QE6 0x00000200
#define MPC85xx_PMUXCR_QE7 0x00000100
#define MPC85xx_PMUXCR_QE8 0x00000080
#define MPC85xx_PMUXCR_QE9 0x00000040
#define MPC85xx_PMUXCR_QE10 0x00000020
#define MPC85xx_PMUXCR_QE11 0x00000010
#define MPC85xx_PMUXCR_QE12 0x00000008
#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
#define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00
#define MPC85xx_PMUXCR_TDM 0x00014800
#define MPC85xx_PMUXCR_SPI_MASK 0x00600000
#define MPC85xx_PMUXCR_SPI 0x00000000
#endif
u32 pmuxcr2; /* Alt. function signal multiplex control 2 */
#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
#define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f1000
#define MPC85xx_PMUXCR2_USB 0x00150000
#endif
u8 res6[8];
u32 devdisr; /* Device disable control */
#define MPC85xx_DEVDISR_PCI1 0x80000000
@ -1956,32 +1980,43 @@ typedef struct ccsr_gur {
u8 res9[12];
u32 pvr; /* Processor version */
u32 svr; /* System version */
u8 res10a[8];
u8 res10[8];
u32 rstcr; /* Reset control */
#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
u8 res10b[76];
u8 res11a[76];
par_io_t qe_par_io[7];
u8 res10c[1600];
u8 res11b[1600];
#elif defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
defined(CONFIG_P1021) || defined(CONFIG_P1025)
u8 res11a[12];
u32 iovselsr;
u8 res11b[60];
par_io_t qe_par_io[3];
u8 res11c[1496];
#else
u8 res10b[1868];
u8 res11a[1868];
#endif
u32 clkdvdr; /* Clock Divide register */
u8 res10d[1532];
u8 res12[1532];
u32 clkocr; /* Clock out select */
u8 res11[12];
u8 res13[12];
u32 ddrdllcr; /* DDR DLL control */
u8 res12[12];
u8 res14[12];
u32 lbcdllcr; /* LBC DLL control */
u8 res13[248];
u8 res15[248];
u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */
u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */
u32 ddrioovcr; /* DDR IO Override Control */
u32 tsec12ioovcr; /* eTSEC 1/2 IO override control */
u32 tsec34ioovcr; /* eTSEC 3/4 IO override control */
u8 res15[61648];
u8 res16[52];
u32 sdhcdcr; /* SDHC debug control register */
u8 res17[61592];
} ccsr_gur_t;
#endif
#define SDHCDCR_CD_INV 0x80000000 /* invert SDHC card detect */
typedef struct serdes_corenet {
struct {
u32 rstctl; /* Reset Control Register */

12
board/freescale/corenet_ds/tlb.c
View file

@ -1,5 +1,5 @@
/*
* Copyright 2008-2010 Freescale Semiconductor, Inc.
* Copyright 2008-2011 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@ -51,9 +51,19 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 1 */
/* *I*** - Covers boot page */
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
/*
* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
* SRAM is at 0xfff00000, it covered the 0xfffff000.
*/
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
#else
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_4K, 1),
#endif
/* *I*G* - CCSRBAR */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,

54
board/freescale/p1022ds/p1022ds.c
View file

@ -93,11 +93,19 @@ int checkboard(void)
/* Choose the 11.2896Mhz codec reference clock */
#define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01
/* Connect to USB2 */
#define CONFIG_PIXIS_BRDCFG0_USB2 0x10
/* Connect to TFM bus */
#define CONFIG_PIXIS_BRDCFG1_TDM 0x0c
/* Connect to SPI */
#define CONFIG_PIXIS_BRDCFG0_SPI 0x80
int misc_init_r(void)
{
u8 temp;
const char *audclk;
size_t arglen;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
/* For DVI, enable the TFP410 Encoder. */
@ -115,22 +123,48 @@ int misc_init_r(void)
return -1;
debug("DVI Encoder Read: 0x%02x\n",temp);
/* Enable the USB2 in PMUXCR2 and FGPA */
if (hwconfig("usb2")) {
clrsetbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_ETSECUSB_MASK,
MPC85xx_PMUXCR2_USB);
setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_USB2);
}
/* tdm and audio can not enable simultaneous*/
if (hwconfig("tdm") && hwconfig("audclk")){
printf("WARNING: TDM and AUDIO can not be enabled simultaneous !\n");
return -1;
}
/* Enable the TDM in PMUXCR and FGPA */
if (hwconfig("tdm")) {
clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_MASK,
MPC85xx_PMUXCR_TDM);
setbits_8(&pixis->brdcfg1, CONFIG_PIXIS_BRDCFG1_TDM);
/* TDM need some configration option by SPI */
clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SPI_MASK,
MPC85xx_PMUXCR_SPI);
setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_SPI);
}
/*
* Enable the reference clock for the WM8776 codec, and route the MUX
* pins for SSI. The default is the 12.288 MHz clock
*/
temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK |
CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
if (hwconfig("audclk")) {
temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK |
CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
audclk = hwconfig_arg("audclk", &arglen);
/* Check the first two chars only */
if (audclk && (strncmp(audclk, "11", 2) == 0))
temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
else
temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
out_8(&pixis->brdcfg1, temp);
audclk = hwconfig_arg("audclk", &arglen);
/* Check the first two chars only */
if (audclk && (strncmp(audclk, "11", 2) == 0))
temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
else
temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
setbits_8(&pixis->brdcfg1, temp);
}
return 0;
}

1
boards.cfg
View file

@ -545,6 +545,7 @@ P2020RDB_NAND powerpc mpc85xx p1_p2_rdb freesca
P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SDCARD
P2020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SPIFLASH
P4080DS powerpc mpc85xx corenet_ds freescale
P4080DS_RAMBOOT_PBL powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF80000
mpq101 powerpc mpc85xx mpq101 mercury - mpq101
stxgp3 powerpc mpc85xx stxgp3 stx
stxssa powerpc mpc85xx stxssa stx - stxssa

24
doc/README.p1022ds Normal file
View file

@ -0,0 +1,24 @@
Overview
--------
P1022ds is a Low End Dual core platform supporting the P1022 processor
of QorIQ series. P1022 is an e500 based dual core SOC.
Pin Multiplex(hwconfig setting)
-------------------------------
Add the environment 'usb2', 'audclk' and 'tdm' to support pin multiplex
via hwconfig, i.e:
'setenv hwconfig usb2' to enable USB2 and disable eTsec2
'setenv hwconfig tdm' to enable TDM and disable Audio
'setenv hwconfig audclk:12' to enable Audio(codec clock sources is 12MHz)
and disable TDM
'setenv hwconfig 'usb2;tdm' to enable USB2 and TDM, disable eTsec2 and Audio
'setenv hwconfig 'usb2;audclk:11' to enable USB2 and Audio(codec clock sources
is 11MHz), disable eTsec2 and TDM
Warning: TDM and AUDIO can not enable simultaneous !
and AUDIO codec clock sources only setting as 11MHz or 12MHz !
'setenv hwconfig 'audclk:12;tdm' --- error !
'setenv hwconfig 'audclk:11;tdm' --- error !
'setenv hwconfig 'audclk:10' --- error !

32
doc/README.p4080ds Normal file
View file

@ -0,0 +1,32 @@
Overview
--------
The P4080DS is a Freescale reference board that hosts the eight-core P4080 SOC.
SerDes hwconfig configuration
-----------------------------
The P4080 RCW includes three sets of bits the specify which SerDes lanes
should be powered down: SRDS_LPD_B1 (for bank one), SRDS_LPD_B2 (for bank two),
and SRDS_LPD_B3 (for bank three). Each of these contains four bits, one for
each lane in the bank. SerDes Erratum SERDES8 requires that SRDS_LPD_B2 and
SRDS_LPD_B3 be set to 0b1111. This forces banks two and three to be powered
down at reset.
To re-enable these banks in U-Boot, two hwconfig are available:
"fsl_srds_lpd_b2" and "fsl_srds_lpd_b3". The value passed via fsl_srds_lpd_b2
is written into SRDS_LPD_B2, and the value passed via fsl_srds_lpd_b3 is into
SRDS_LPD_B3. Each bit represents one of each bank, and a value of '1'
indicates that the lane should be powered down.
For example, to indicate that both SerDes banks 2 and 3 are powered down, add
the following to hwconfig:
serdes:fsl_srds_lpd_b2=0xf,fsl_srds_lpd_b3=0xf
The "0xf" is a mask that corresponds to the 4 lanes A-D. The most significant
bit corresponds to lane A. To indicate that just lane A of bank 3 is to be
powered down, use:
serdes:fsl_srds_lpd_b3=8
These options should be specified only if U-Boot does not automatically power
on the correct lanes.

8
drivers/mmc/fsl_esdhc.c
View file

@ -178,14 +178,14 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
wml_value = data->blocksize/4;
if (data->flags & MMC_DATA_READ) {
if (wml_value > 0x10)
wml_value = 0x10;
if (wml_value > WML_RD_WML_MAX)
wml_value = WML_RD_WML_MAX_VAL;
esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
esdhc_write32(&regs->dsaddr, (u32)data->dest);
} else {
if (wml_value > 0x80)
wml_value = 0x80;
if (wml_value > WML_WR_WML_MAX)
wml_value = WML_WR_WML_MAX_VAL;
if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
return TIMEOUT;

37
drivers/qe/uec.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (C) 2006-2010 Freescale Semiconductor, Inc.
* Copyright (C) 2006-2011 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
*
@ -588,9 +588,27 @@ static void phy_change(struct eth_device *dev)
{
uec_private_t *uec = (uec_private_t *)dev->priv;
#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
defined(CONFIG_P1021) || defined(CONFIG_P1025)
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
/* QE9 and QE12 need to be set for enabling QE MII managment signals */
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
#endif
/* Update the link, speed, duplex */
uec->mii_info->phyinfo->read_status(uec->mii_info);
#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
defined(CONFIG_P1021) || defined(CONFIG_P1025)
/*
* QE12 is muxed with LBCTL, it needs to be released for enabling
* LBCTL signal for LBC usage.
*/
clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
#endif
/* Adjust the interface according to speed */
adjust_link(dev);
}
@ -1198,10 +1216,21 @@ static int uec_init(struct eth_device* dev, bd_t *bd)
uec_private_t *uec;
int err, i;
struct phy_info *curphy;
#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
defined(CONFIG_P1021) || defined(CONFIG_P1025)
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
uec = (uec_private_t *)dev->priv;
if (uec->the_first_run == 0) {
#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
defined(CONFIG_P1021) || defined(CONFIG_P1025)
/* QE9 and QE12 need to be set for enabling QE MII managment signals */
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
#endif
err = init_phy(dev);
if (err) {
printf("%s: Cannot initialize PHY, aborting.\n",
@ -1228,6 +1257,12 @@ static int uec_init(struct eth_device* dev, bd_t *bd)
udelay(100000);
} while (1);
#if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
defined(CONFIG_P1021) || defined(CONFIG_P1025)
/* QE12 needs to be released for enabling LBCTL signal*/
clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
#endif
if (err || i <= 0)
printf("warning: %s: timeout on PHY link\n", dev->name);

18
include/configs/MPC8536DS.h
View file

@ -361,13 +361,13 @@
#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
/* NAND flash config */
#define CONFIG_NAND_BR_PRELIM \
#define CONFIG_SYS_NAND_BR_PRELIM \
(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
| OR_FCM_PGS /* Large Page*/ \
| OR_FCM_CSCT \
| OR_FCM_CST \
@ -377,15 +377,15 @@
| OR_FCM_EHTR)
#ifdef CONFIG_RAMBOOT_NAND
#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
#else
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#endif
#define CONFIG_SYS_BR4_PRELIM \
@ -394,14 +394,14 @@
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR5_PRELIM \
(BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR6_PRELIM \
(BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)) \
@ -409,7 +409,7 @@
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
/* Serial Port - controlled on board with jumper J8
* open - index 2

12
include/configs/MPC8569MDS.h
View file

@ -240,12 +240,12 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_CHT \
@ -254,15 +254,15 @@ extern unsigned long get_clock_freq(void);
| OR_FCM_EHTR)
#ifdef CONFIG_RAMBOOT_NAND
#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM/* NAND Options */
#define CONFIG_SYS_BR3_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR3_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
#else
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
#define CONFIG_SYS_BR3_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR3_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#endif
#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */

18
include/configs/MPC8572DS.h
View file

@ -362,12 +362,12 @@
/* NAND flash config */
#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
| OR_FCM_PGS /* Large Page*/ \
| OR_FCM_CSCT \
| OR_FCM_CST \
@ -377,35 +377,35 @@
| OR_FCM_EHTR)
#ifdef CONFIG_RAMBOOT_NAND
#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
#else
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#endif
#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
/* Serial Port - controlled on board with jumper J8

17
include/configs/P1022DS.h
View file

@ -219,6 +219,22 @@
#undef CONFIG_SYS_FLASH_EMPTY_INFO
#endif
#ifndef CONFIG_DIU
#define CONFIG_ATI
#endif
#ifdef CONFIG_ATI
#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
#define CONFIG_VIDEO
#define CONFIG_BIOSEMU
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_ATI_RADEON_FB
#define CONFIG_VIDEO_LOGO
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
#endif
/*
* Pass open firmware flat tree
*/
@ -492,6 +508,7 @@
"dium=mw e002c01c\0" \
"diuerr=md e002c014 1\0" \
"othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 tty0\0" \
"hwconfig=esdhc;audclk:12\0" \
"monitor=0-DVI\0"
#define CONFIG_HDBOOT \

12
include/configs/P1_P2_RDB.h
View file

@ -303,13 +303,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
/* NAND flash config */
#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \
#define CONFIG_SYS_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_CHT \
@ -318,15 +318,15 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
| OR_FCM_EHTR)
#ifdef CONFIG_RAMBOOT_NAND
#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
#else
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
#define CONFIG_SYS_BR1_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR1_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#endif
#define CONFIG_SYS_VSC7385_BASE 0xffb00000

14
include/configs/P2020DS.h
View file

@ -326,12 +326,12 @@
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
/* NAND flash config */
#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
| OR_FCM_PGS /* Large Page*/ \
| OR_FCM_CSCT \
| OR_FCM_CST \
@ -342,28 +342,28 @@
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
/* Serial Port - controlled on board with jumper J8
* open - index 2

50
include/configs/corenet_ds.h
View file

@ -28,6 +28,11 @@
#include "../board/freescale/common/ics307_clk.h"
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif
/* High Level Configuration Options */
#define CONFIG_BOOKE
#define CONFIG_E500 /* BOOKE e500 family */
@ -63,12 +68,17 @@
#define CONFIG_ENV_OVERWRITE
#if defined(CONFIG_RAMBOOT_PBL)
#define CONFIG_SYS_NO_FLASH /* Store ENV in memory only */
#endif
#ifdef CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_IS_NOWHERE
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
@ -99,6 +109,18 @@
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_PANIC_HANG /* do not reset board on panic */
/*
* Config the L3 Cache as L3 SRAM
*/
#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
#else
#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
#endif
#define CONFIG_SYS_L3_SIZE (1024 << 10)
#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
@ -192,6 +214,10 @@
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#if defined(CONFIG_RAMBOOT_PBL)
#define CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
@ -390,33 +416,10 @@
#endif
#ifdef CONFIG_PCI
/*PCIE video card used*/
#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
/* video */
#define CONFIG_VIDEO
#ifdef CONFIG_VIDEO
#define CONFIG_BIOSEMU
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_ATI_RADEON_FB
#define CONFIG_VIDEO_LOGO
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
#endif
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_E1000
#ifndef CONFIG_PCI_PNP
#define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
#define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
#define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_DOS_PARTITION
#endif /* CONFIG_PCI */
@ -462,7 +465,6 @@
/*
* Environment
*/
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */

15
include/fsl_esdhc.h
View file

@ -2,7 +2,7 @@
* FSL SD/MMC Defines
*-------------------------------------------------------------------
*
* Copyright 2007-2008,2010 Freescale Semiconductor, Inc
* Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -135,8 +135,21 @@
#define WML 0x2e044
#define WML_WRITE 0x00010000
#ifdef CONFIG_FSL_SDHC_V2_3
#define WML_RD_WML_MAX 0x80
#define WML_WR_WML_MAX 0x80
#define WML_RD_WML_MAX_VAL 0x0
#define WML_WR_WML_MAX_VAL 0x0
#define WML_RD_WML_MASK 0x7f
#define WML_WR_WML_MASK 0x7f0000
#else
#define WML_RD_WML_MAX 0x10
#define WML_WR_WML_MAX 0x80
#define WML_RD_WML_MAX_VAL 0x10
#define WML_WR_WML_MAX_VAL 0x80
#define WML_RD_WML_MASK 0xff
#define WML_WR_WML_MASK 0xff0000
#endif
#define BLKATTR 0x2e004
#define BLKATTR_CNT(x) ((x & 0xffff) << 16)