driver/ddr/fsl: Update DDR4 MR6 for Vref range
MR6 bit 6 is set accrodingly for range 1 or 2, per JEDEC spec. Signed-off-by: York Sun <yorksun@freescale.com>
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@ -1186,6 +1186,9 @@ static void set_ddr_sdram_mode_10(const unsigned int ctrl_num,
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esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
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if (popts->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
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esdmode6 |= 1 << 6; /* Range 2 */
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ddr->ddr_sdram_mode_10 = (0
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| ((esdmode6 & 0xffff) << 16)
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| ((esdmode7 & 0xffff) << 0)
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