board: verdin-imx8mp: compact slight different lpddr4 configuration
Deduplicate similar DDRC configurations and LPDDR4 training patterns by patching a single configuration. The aim is to reduce the SPL memory footprint and simplify maintenance of lpddr4_timing.c Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
This commit is contained in:
Emanuele Ghidoli
Stefano Babic
parent
390bb9fcc0
commit
0e897621b4
3 changed files with 75 additions and 322 deletions
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@ -13,6 +13,33 @@
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#include <linux/kernel.h>
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#include <asm/arch/ddr.h>
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#include "lpddr4_timing.h"
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struct dram_cfg_param ddr_ddrc_cfg_single_rank_patch[] = {
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{ 0x3d400000, 0xa1080020},
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{ 0x3d400200, 0x1f},
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{ 0x3d40021c, 0xf07}
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};
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struct dram_cfg_param ddr_fsp0_cfg_single_rank_patch[] = {
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{ 0x54012, 0x110},
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{ 0x5402c, 0x1}
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};
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struct dram_cfg_param ddr_fsp1_cfg_single_rank_patch[] = {
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{ 0x54012, 0x110},
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{ 0x5402c, 0x1}
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};
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struct dram_cfg_param ddr_fsp2_cfg_single_rank_patch[] = {
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{ 0x54012, 0x110},
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{ 0x5402c, 0x1}
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};
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struct dram_cfg_param ddr_fsp0_2d_cfg_single_rank_patch[] = {
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{ 0x54012, 0x110},
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{ 0x5402c, 0x1}
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};
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struct dram_cfg_param ddr_ddrc_cfg[] = {
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/** Initialize DDRC registers **/
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@ -1835,311 +1862,7 @@ struct dram_fsp_msg ddr_dram_fsp_msg[] = {
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},
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};
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struct dram_cfg_param ddr_ddrc_cfg2[] = {
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/** Initialize DDRC registers **/
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{ 0x3d400304, 0x1 },
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{ 0x3d400030, 0x1 },
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{ 0x3d400000, 0xa1080020 },
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{ 0x3d400020, 0x1303 },
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{ 0x3d400024, 0x1e84800 },
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{ 0x3d400064, 0x7a017c },
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{ 0x3d400070, 0x7027f90 },
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{ 0x3d400074, 0x790 },
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{ 0x3d4000d0, 0xc00307a3 },
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{ 0x3d4000d4, 0xc50000 },
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{ 0x3d4000dc, 0xf4003f },
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{ 0x3d4000e0, 0x330000 },
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{ 0x3d4000e8, 0x660048 },
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{ 0x3d4000ec, 0x160048 },
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{ 0x3d400100, 0x2028222a },
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{ 0x3d400104, 0x8083f },
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{ 0x3d40010c, 0xe0e000 },
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{ 0x3d400110, 0x12040a12 },
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{ 0x3d400114, 0x2050f0f },
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{ 0x3d400118, 0x1010009 },
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{ 0x3d40011c, 0x502 },
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{ 0x3d400130, 0x20800 },
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{ 0x3d400134, 0xe100002 },
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{ 0x3d400138, 0x184 },
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{ 0x3d400144, 0xc80064 },
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{ 0x3d400180, 0x3e8001e },
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{ 0x3d400184, 0x3207a12 },
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{ 0x3d400188, 0x0 },
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{ 0x3d400190, 0x49f820e },
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{ 0x3d400194, 0x80303 },
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{ 0x3d4001b4, 0x1f0e },
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{ 0x3d4001a0, 0xe0400018 },
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{ 0x3d4001a4, 0xdf00e4 },
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{ 0x3d4001a8, 0x80000000 },
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{ 0x3d4001b0, 0x11 },
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{ 0x3d4001c0, 0x1 },
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{ 0x3d4001c4, 0x1 },
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{ 0x3d4000f4, 0x799 },
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{ 0x3d400108, 0x9121b1c },
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{ 0x3d400200, 0x1f },
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{ 0x3d400208, 0x0 },
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{ 0x3d40020c, 0x0 },
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{ 0x3d400210, 0x1f1f },
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{ 0x3d400204, 0x80808 },
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{ 0x3d400214, 0x7070707 },
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{ 0x3d400218, 0x7070707 },
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{ 0x3d40021c, 0xf07 },
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{ 0x3d400250, 0x1705 },
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{ 0x3d400254, 0x2c },
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{ 0x3d40025c, 0x4000030 },
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{ 0x3d400264, 0x900093e7 },
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{ 0x3d40026c, 0x2005574 },
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{ 0x3d400400, 0x111 },
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{ 0x3d400404, 0x72ff },
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{ 0x3d400408, 0x72ff },
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{ 0x3d400494, 0x2100e07 },
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{ 0x3d400498, 0x620096 },
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{ 0x3d40049c, 0x1100e07 },
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{ 0x3d4004a0, 0xc8012c },
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{ 0x3d402020, 0x1001 },
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{ 0x3d402024, 0x30d400 },
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{ 0x3d402050, 0x20d000 },
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{ 0x3d402064, 0xc0026 },
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{ 0x3d4020dc, 0x840000 },
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{ 0x3d4020e0, 0x330000 },
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{ 0x3d4020e8, 0x660048 },
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{ 0x3d4020ec, 0x160048 },
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{ 0x3d402100, 0xa040305 },
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{ 0x3d402104, 0x30407 },
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{ 0x3d402108, 0x203060b },
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{ 0x3d40210c, 0x505000 },
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{ 0x3d402110, 0x2040202 },
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{ 0x3d402114, 0x2030202 },
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{ 0x3d402118, 0x1010004 },
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{ 0x3d40211c, 0x302 },
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{ 0x3d402130, 0x20300 },
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{ 0x3d402134, 0xa100002 },
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{ 0x3d402138, 0x27 },
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{ 0x3d402144, 0x14000a },
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{ 0x3d402180, 0x640004 },
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{ 0x3d402190, 0x3818200 },
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{ 0x3d402194, 0x80303 },
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{ 0x3d4021b4, 0x100 },
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{ 0x3d4020f4, 0x599 },
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{ 0x3d403020, 0x1001 },
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{ 0x3d403024, 0xc3500 },
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{ 0x3d403050, 0x20d000 },
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{ 0x3d403064, 0x3000a },
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{ 0x3d4030dc, 0x840000 },
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{ 0x3d4030e0, 0x330000 },
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{ 0x3d4030e8, 0x660048 },
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{ 0x3d4030ec, 0x160048 },
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{ 0x3d403100, 0xa010102 },
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{ 0x3d403104, 0x30404 },
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{ 0x3d403108, 0x203060b },
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{ 0x3d40310c, 0x505000 },
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{ 0x3d403110, 0x2040202 },
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{ 0x3d403114, 0x2030202 },
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{ 0x3d403118, 0x1010004 },
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{ 0x3d40311c, 0x302 },
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{ 0x3d403130, 0x20300 },
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{ 0x3d403134, 0xa100002 },
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{ 0x3d403138, 0xa },
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{ 0x3d403144, 0x50003 },
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{ 0x3d403180, 0x190004 },
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{ 0x3d403190, 0x3818200 },
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{ 0x3d403194, 0x80303 },
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{ 0x3d4031b4, 0x100 },
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{ 0x3d4030f4, 0x599 },
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{ 0x3d400028, 0x0 },
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};
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/* P0 message block parameter for training firmware */
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struct dram_cfg_param ddr_fsp0_cfg2[] = {
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{ 0xd0000, 0x0 },
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{ 0x54003, 0xfa0 },
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{ 0x54004, 0x2 },
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{ 0x54005, 0x2228 },
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{ 0x54006, 0x14 },
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{ 0x54008, 0x131f },
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{ 0x54009, 0xc8 },
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{ 0x5400b, 0x2 },
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{ 0x5400f, 0x100 },
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{ 0x54012, 0x110 },
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{ 0x54019, 0x3ff4 },
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{ 0x5401a, 0x33 },
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{ 0x5401b, 0x4866 },
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{ 0x5401c, 0x4800 },
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{ 0x5401e, 0x16 },
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{ 0x5401f, 0x3ff4 },
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{ 0x54020, 0x33 },
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{ 0x54021, 0x4866 },
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{ 0x54022, 0x4800 },
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{ 0x54024, 0x16 },
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{ 0x5402b, 0x1000 },
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{ 0x5402c, 0x1 },
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{ 0x54032, 0xf400 },
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{ 0x54033, 0x333f },
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{ 0x54034, 0x6600 },
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{ 0x54035, 0x48 },
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{ 0x54036, 0x48 },
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{ 0x54037, 0x1600 },
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{ 0x54038, 0xf400 },
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{ 0x54039, 0x333f },
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{ 0x5403a, 0x6600 },
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{ 0x5403b, 0x48 },
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{ 0x5403c, 0x48 },
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{ 0x5403d, 0x1600 },
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{ 0xd0000, 0x1 },
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};
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/* P1 message block parameter for training firmware */
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struct dram_cfg_param ddr_fsp1_cfg2[] = {
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{ 0xd0000, 0x0 },
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{ 0x54002, 0x101 },
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{ 0x54003, 0x190 },
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{ 0x54004, 0x2 },
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{ 0x54005, 0x2228 },
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{ 0x54006, 0x14 },
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{ 0x54008, 0x121f },
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{ 0x54009, 0xc8 },
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{ 0x5400b, 0x2 },
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{ 0x5400f, 0x100 },
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{ 0x54012, 0x110 },
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{ 0x54019, 0x84 },
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{ 0x5401a, 0x33 },
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{ 0x5401b, 0x4866 },
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{ 0x5401c, 0x4800 },
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{ 0x5401e, 0x16 },
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{ 0x5401f, 0x84 },
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{ 0x54020, 0x33 },
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{ 0x54021, 0x4866 },
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{ 0x54022, 0x4800 },
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{ 0x54024, 0x16 },
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{ 0x5402b, 0x1000 },
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{ 0x5402c, 0x1 },
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{ 0x54032, 0x8400 },
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{ 0x54033, 0x3300 },
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{ 0x54034, 0x6600 },
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{ 0x54035, 0x48 },
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{ 0x54036, 0x48 },
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{ 0x54037, 0x1600 },
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{ 0x54038, 0x8400 },
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{ 0x54039, 0x3300 },
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{ 0x5403a, 0x6600 },
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{ 0x5403b, 0x48 },
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{ 0x5403c, 0x48 },
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{ 0x5403d, 0x1600 },
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{ 0xd0000, 0x1 },
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};
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/* P2 message block parameter for training firmware */
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struct dram_cfg_param ddr_fsp2_cfg2[] = {
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{ 0xd0000, 0x0 },
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{ 0x54002, 0x102 },
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{ 0x54003, 0x64 },
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{ 0x54004, 0x2 },
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{ 0x54005, 0x2228 },
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{ 0x54006, 0x14 },
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{ 0x54008, 0x121f },
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{ 0x54009, 0xc8 },
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{ 0x5400b, 0x2 },
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{ 0x5400f, 0x100 },
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{ 0x54012, 0x110 },
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{ 0x54019, 0x84 },
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{ 0x5401a, 0x33 },
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{ 0x5401b, 0x4866 },
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{ 0x5401c, 0x4800 },
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{ 0x5401e, 0x16 },
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{ 0x5401f, 0x84 },
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{ 0x54020, 0x33 },
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{ 0x54021, 0x4866 },
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{ 0x54022, 0x4800 },
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{ 0x54024, 0x16 },
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{ 0x5402b, 0x1000 },
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{ 0x5402c, 0x1 },
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{ 0x54032, 0x8400 },
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{ 0x54033, 0x3300 },
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{ 0x54034, 0x6600 },
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{ 0x54035, 0x48 },
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{ 0x54036, 0x48 },
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{ 0x54037, 0x1600 },
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{ 0x54038, 0x8400 },
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{ 0x54039, 0x3300 },
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{ 0x5403a, 0x6600 },
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{ 0x5403b, 0x48 },
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{ 0x5403c, 0x48 },
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{ 0x5403d, 0x1600 },
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{ 0xd0000, 0x1 },
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};
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/* P0 2D message block parameter for training firmware */
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struct dram_cfg_param ddr_fsp0_2d_cfg2[] = {
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{ 0xd0000, 0x0 },
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{ 0x54003, 0xfa0 },
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{ 0x54004, 0x2 },
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{ 0x54005, 0x2228 },
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{ 0x54006, 0x14 },
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{ 0x54008, 0x61 },
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{ 0x54009, 0xc8 },
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{ 0x5400b, 0x2 },
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{ 0x5400f, 0x100 },
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{ 0x54010, 0x1f7f },
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{ 0x54012, 0x110 },
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{ 0x54019, 0x3ff4 },
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{ 0x5401a, 0x33 },
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{ 0x5401b, 0x4866 },
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{ 0x5401c, 0x4800 },
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{ 0x5401e, 0x16 },
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{ 0x5401f, 0x3ff4 },
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{ 0x54020, 0x33 },
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{ 0x54021, 0x4866 },
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{ 0x54022, 0x4800 },
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{ 0x54024, 0x16 },
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{ 0x5402b, 0x1000 },
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{ 0x5402c, 0x1 },
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{ 0x54032, 0xf400 },
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{ 0x54033, 0x333f },
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{ 0x54034, 0x6600 },
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{ 0x54035, 0x48 },
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{ 0x54036, 0x48 },
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{ 0x54037, 0x1600 },
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{ 0x54038, 0xf400 },
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{ 0x54039, 0x333f },
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{ 0x5403a, 0x6600 },
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{ 0x5403b, 0x48 },
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{ 0x5403c, 0x48 },
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{ 0x5403d, 0x1600 },
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{ 0xd0000, 0x1 },
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};
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struct dram_fsp_msg ddr_dram_fsp_msg2[] = {
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{
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/* P0 4000mts 1D */
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.drate = 4000,
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.fw_type = FW_1D_IMAGE,
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.fsp_cfg = ddr_fsp0_cfg2,
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.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg2),
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},
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{
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/* P1 400mts 1D */
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.drate = 400,
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.fw_type = FW_1D_IMAGE,
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.fsp_cfg = ddr_fsp1_cfg2,
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.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg2),
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},
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{
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/* P2 100mts 1D */
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.drate = 100,
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.fw_type = FW_1D_IMAGE,
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.fsp_cfg = ddr_fsp2_cfg2,
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.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg2),
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},
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{
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/* P0 4000mts 2D */
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.drate = 4000,
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.fw_type = FW_2D_IMAGE,
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.fsp_cfg = ddr_fsp0_2d_cfg2,
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.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg2),
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},
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};
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/* quad die, dual rank aka 8 GB DDR timing config params */
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/* ddr timing config params */
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struct dram_timing_info dram_timing = {
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.ddrc_cfg = ddr_ddrc_cfg,
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.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
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@ -2154,17 +1877,36 @@ struct dram_timing_info dram_timing = {
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.fsp_table = { 4000, 400, 100, },
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};
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/* dual die, single rank aka 1 GB (untested), 2 GB or 4 GB DDR timing config params */
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struct dram_timing_info dram_timing2 = {
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.ddrc_cfg = ddr_ddrc_cfg2,
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.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg2),
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.ddrphy_cfg = ddr_ddrphy_cfg,
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.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
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.fsp_msg = ddr_dram_fsp_msg2,
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.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg2),
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.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
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.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
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.ddrphy_pie = ddr_phy_pie,
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.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
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.fsp_table = { 4000, 400, 100, },
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};
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static void apply_cfg_patch(struct dram_cfg_param *cfg, int cfg_sz,
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struct dram_cfg_param *patch, int patch_sz)
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{
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int i, j;
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for (i = 0; i < cfg_sz; i++)
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for (j = 0; j < patch_sz; j++)
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if (cfg[i].reg == patch[j].reg)
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cfg[i].val = patch[j].val;
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}
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void lpddr4_single_rank_training_patch(void)
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{
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apply_cfg_patch(ddr_ddrc_cfg, ARRAY_SIZE(ddr_ddrc_cfg),
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ddr_ddrc_cfg_single_rank_patch,
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ARRAY_SIZE(ddr_ddrc_cfg_single_rank_patch));
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apply_cfg_patch(ddr_fsp0_cfg, ARRAY_SIZE(ddr_fsp0_cfg),
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ddr_fsp0_cfg_single_rank_patch,
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ARRAY_SIZE(ddr_fsp0_cfg_single_rank_patch));
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apply_cfg_patch(ddr_fsp1_cfg, ARRAY_SIZE(ddr_fsp1_cfg),
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ddr_fsp1_cfg_single_rank_patch,
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ARRAY_SIZE(ddr_fsp1_cfg_single_rank_patch));
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||||
apply_cfg_patch(ddr_fsp2_cfg, ARRAY_SIZE(ddr_fsp2_cfg),
|
||||
ddr_fsp2_cfg_single_rank_patch,
|
||||
ARRAY_SIZE(ddr_fsp2_cfg_single_rank_patch));
|
||||
|
||||
apply_cfg_patch(ddr_fsp0_2d_cfg, ARRAY_SIZE(ddr_fsp0_2d_cfg),
|
||||
ddr_fsp0_2d_cfg_single_rank_patch,
|
||||
ARRAY_SIZE(ddr_fsp0_2d_cfg_single_rank_patch));
|
||||
}
|
||||
|
|
|
|||
11
board/toradex/verdin-imx8mp/lpddr4_timing.h
Normal file
11
board/toradex/verdin-imx8mp/lpddr4_timing.h
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* Copyright 2022 Toradex
|
||||
*/
|
||||
|
||||
#ifndef __LPDDR4_TIMING_H__
|
||||
#define __LPDDR4_TIMING_H__
|
||||
|
||||
void lpddr4_single_rank_training_patch(void);
|
||||
|
||||
#endif /* __LPDDR4_TIMING_H__ */
|
||||
|
|
@ -21,8 +21,7 @@
|
|||
#include <dm/uclass.h>
|
||||
#include <power/pmic.h>
|
||||
#include <power/pca9450.h>
|
||||
|
||||
extern struct dram_timing_info dram_timing2;
|
||||
#include "lpddr4_timing.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
|
@ -38,7 +37,8 @@ void spl_dram_init(void)
|
|||
*/
|
||||
if (ddr_init(&dram_timing)) {
|
||||
printf("Dual rank failed, attempting single rank configuration.\n");
|
||||
ddr_init(&dram_timing2);
|
||||
lpddr4_single_rank_training_patch();
|
||||
ddr_init(&dram_timing);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue