arm: dts: qcom: Sync pinctrl DT nodes with Linux bindings
Currently for all Qcom SoCs/boards there are separate compatibles for GPIO and pinctrl. But this is inconsistent with official (upstream) Linux bindings which requires only a single compatible "qcom,<SoC name>-pinctrl" and there is no such compatible property as "qcom,tlmm-<SoC name>". So fix this inconsistency for Qcom SoCs in order to comply with upstream DT bindings. This is done via removing compatibles from "msm_gpio" driver and via binding to "msm_gpio" driver from pinctrl driver in case "gpio-controller" property is specified for pinctrl node. Suggested-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
This commit is contained in:
Sumit Garg
Tom Rini
parent
a4b99582bb
commit
0ddabb6830
10 changed files with 82 additions and 43 deletions
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@ -14,7 +14,7 @@
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soc {
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u-boot,dm-pre-reloc;
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qcom,tlmm@1000000 {
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pinctrl@1000000 {
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u-boot,dm-pre-reloc;
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uart {
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@ -60,9 +60,13 @@
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reg = <0x60000 0x8000>;
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};
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pinctrl: qcom,tlmm@1000000 {
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compatible = "qcom,tlmm-apq8016";
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soc_gpios: pinctrl@1000000 {
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compatible = "qcom,msm8916-pinctrl";
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reg = <0x1000000 0x400000>;
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gpio-controller;
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gpio-count = <122>;
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gpio-bank-name="soc";
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#gpio-cells = <2>;
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blsp1_uart: uart {
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function = "blsp1_uart";
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@ -86,15 +90,6 @@
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pinctrl-0 = <&blsp1_uart>;
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};
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soc_gpios: pinctrl@1000000 {
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compatible = "qcom,apq8016-pinctrl";
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reg = <0x1000000 0x300000>;
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gpio-controller;
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gpio-count = <122>;
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gpio-bank-name="soc";
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#gpio-cells = <2>;
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};
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ehci@78d9000 {
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compatible = "qcom,ehci-host";
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reg = <0x78d9000 0x400>;
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@ -13,7 +13,7 @@
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soc {
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u-boot,dm-pre-reloc;
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qcom,tlmm@1010000 {
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pinctrl@1010000 {
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u-boot,dm-pre-reloc;
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uart {
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@ -64,8 +64,8 @@
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reg = <0x300000 0x90000>;
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};
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pinctrl: qcom,tlmm@1010000 {
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compatible = "qcom,tlmm-apq8096";
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pinctrl: pinctrl@1010000 {
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compatible = "qcom,msm8996-pinctrl";
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reg = <0x1010000 0x400000>;
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blsp8_uart: uart {
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@ -75,9 +75,13 @@
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u-boot,dm-pre-reloc;
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};
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pinctrl: qcom,tlmm@1000000 {
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compatible = "qcom,tlmm-ipq4019";
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soc_gpios: pinctrl@1000000 {
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compatible = "qcom,ipq4019-pinctrl";
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reg = <0x1000000 0x300000>;
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gpio-controller;
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gpio-count = <100>;
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gpio-bank-name="soc";
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#gpio-cells = <2>;
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u-boot,dm-pre-reloc;
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};
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@ -90,16 +94,6 @@
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u-boot,dm-pre-reloc;
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};
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soc_gpios: pinctrl@1000000 {
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compatible = "qcom,ipq4019-pinctrl";
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reg = <0x1000000 0x300000>;
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gpio-controller;
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gpio-count = <100>;
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gpio-bank-name="soc";
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#gpio-cells = <2>;
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u-boot,dm-pre-reloc;
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};
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blsp1_spi1: spi@78b5000 {
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compatible = "qcom,spi-qup-v2.2.1";
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reg = <0x78b5000 0x600>;
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@ -38,7 +38,7 @@
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compatible = "simple-bus";
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pinctrl_north@1300000 {
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compatible = "qcom,tlmm-qcs404";
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compatible = "qcom,qcs404-pinctrl";
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reg = <0x1300000 0x200000>;
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blsp1_uart2: uart {
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@ -37,7 +37,7 @@
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};
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tlmm_north: pinctrl_north@3900000 {
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compatible = "qcom,tlmm-sdm845";
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compatible = "qcom,sdm845-pinctrl";
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reg = <0x3900000 0x400000>;
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gpio-count = <150>;
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gpio-controller;
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@ -14,6 +14,8 @@
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#include <dm.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include <dm/lists.h>
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#include <dm/pinctrl.h>
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#include <linux/bitops.h>
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#include "pinctrl-snapdragon.h"
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@ -110,6 +112,32 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector,
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return 0;
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}
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static int msm_pinctrl_bind(struct udevice *dev)
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{
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ofnode node = dev_ofnode(dev);
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const char *name;
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int ret;
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ofnode_get_property(node, "gpio-controller", &ret);
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if (ret < 0)
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return 0;
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/* Get the name of gpio node */
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name = ofnode_get_name(node);
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if (!name)
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return -EINVAL;
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/* Bind gpio node */
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ret = device_bind_driver_to_node(dev, "gpio_msm",
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name, node, NULL);
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if (ret)
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return ret;
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dev_dbg(dev, "bind %s\n", name);
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return 0;
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}
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static struct pinctrl_ops msm_pinctrl_ops = {
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.get_pins_count = msm_get_pins_count,
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.get_pin_name = msm_get_pin_name,
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@ -123,7 +151,7 @@ static struct pinctrl_ops msm_pinctrl_ops = {
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};
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static const struct udevice_id msm_pinctrl_ids[] = {
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{ .compatible = "qcom,tlmm-ipq4019", .data = (ulong)&ipq4019_data },
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{ .compatible = "qcom,ipq4019-pinctrl", .data = (ulong)&ipq4019_data },
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{ }
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};
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@ -134,4 +162,5 @@ U_BOOT_DRIVER(pinctrl_snapdraon) = {
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.priv_auto = sizeof(struct msm_pinctrl_priv),
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.ops = &msm_pinctrl_ops,
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.probe = msm_pinctrl_probe,
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.bind = msm_pinctrl_bind,
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};
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@ -10,6 +10,8 @@
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#include <dm.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include <dm/lists.h>
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#include <dm/pinctrl.h>
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#include <linux/bitops.h>
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#include "pinctrl-snapdragon.h"
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@ -113,11 +115,37 @@ static struct pinctrl_ops msm_pinctrl_ops = {
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.get_function_name = msm_get_function_name,
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};
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static int msm_pinctrl_bind(struct udevice *dev)
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{
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ofnode node = dev_ofnode(dev);
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const char *name;
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int ret;
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ofnode_get_property(node, "gpio-controller", &ret);
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if (ret < 0)
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return 0;
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/* Get the name of gpio node */
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name = ofnode_get_name(node);
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if (!name)
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return -EINVAL;
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/* Bind gpio node */
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ret = device_bind_driver_to_node(dev, "gpio_msm",
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name, node, NULL);
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if (ret)
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return ret;
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dev_dbg(dev, "bind %s\n", name);
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return 0;
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}
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static const struct udevice_id msm_pinctrl_ids[] = {
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{ .compatible = "qcom,tlmm-apq8016", .data = (ulong)&apq8016_data },
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{ .compatible = "qcom,tlmm-apq8096", .data = (ulong)&apq8096_data },
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{ .compatible = "qcom,tlmm-sdm845", .data = (ulong)&sdm845_data },
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{ .compatible = "qcom,tlmm-qcs404", .data = (ulong)&qcs404_data },
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{ .compatible = "qcom,msm8916-pinctrl", .data = (ulong)&apq8016_data },
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{ .compatible = "qcom,msm8996-pinctrl", .data = (ulong)&apq8096_data },
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{ .compatible = "qcom,sdm845-pinctrl", .data = (ulong)&sdm845_data },
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{ .compatible = "qcom,qcs404-pinctrl", .data = (ulong)&qcs404_data },
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{ }
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};
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@ -128,4 +156,5 @@ U_BOOT_DRIVER(pinctrl_snapdraon) = {
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.priv_auto = sizeof(struct msm_pinctrl_priv),
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.ops = &msm_pinctrl_ops,
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.probe = msm_pinctrl_probe,
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.bind = msm_pinctrl_bind,
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};
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@ -116,20 +116,12 @@ static int msm_gpio_of_to_plat(struct udevice *dev)
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return 0;
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}
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static const struct udevice_id msm_gpio_ids[] = {
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{ .compatible = "qcom,msm8916-pinctrl" },
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{ .compatible = "qcom,apq8016-pinctrl" },
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{ .compatible = "qcom,ipq4019-pinctrl" },
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{ .compatible = "qcom,sdm845-pinctrl" },
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{ }
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};
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U_BOOT_DRIVER(gpio_msm) = {
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.name = "gpio_msm",
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.id = UCLASS_GPIO,
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.of_match = msm_gpio_ids,
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.of_to_plat = msm_gpio_of_to_plat,
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.probe = msm_gpio_probe,
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.ops = &gpio_msm_ops,
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.flags = DM_UC_FLAG_SEQ_ALIAS,
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.priv_auto = sizeof(struct msm_gpio_bank),
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};
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