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armv8: fsl-lsch2: add clock support for the second eSDHC

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Layerscape began to use two eSDHC controllers, for example,
LS1012A. They are same IP block with same reference clock.
This patch is to add clock support for the second eSDHC.

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This commit is contained in:
Yinbo Zhu 2019-06-03 19:24:23 +08:00 committed by Prabhakar Kushwaha
parent fd90b6d5ab
commit 0dd74ec2df
1 changed files with 2 additions and 0 deletions
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2
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
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@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor, Inc.
* Copyright 2019 NXP.
*/
#include <common.h>
@ -250,6 +251,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
return get_i2c_freq(0);
#if defined(CONFIG_FSL_ESDHC)
case MXC_ESDHC_CLK:
case MXC_ESDHC2_CLK:
return get_sdhc_freq(0);
#endif
case MXC_DSPI_CLK: