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t104xrdb: Add Errata A_007662, A_008007 workaround in pbi.cfg

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-A_007662 states that for x1 link width, PCIe2 controller trains in
 Gen1 speed while configured for Gen2 speed.
 Workaround:Set the width to x1 and speed to Gen2 by writing to
 CCSR registers in PBI phase

-A_008007 states that PVR register may show random value.
 Workaround: Reset PVR register using DCSR space in PBI phase

Add PBI based software workaround for A_007662 and A_008007
in t104x_pbi.cfg. This is required for SPL-based bootloaders
like NAND-boot, SD-boot, SPI-boot

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Priyanka Jain 2014-09-17 15:57:54 +05:30 committed by York Sun
parent ab06b236f7
commit 0921de6744
1 changed files with 10 additions and 0 deletions
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10
board/freescale/t104xrdb/t104x_pbi.cfg
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@ -1,4 +1,14 @@
#PBI commands #PBI commands
#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed
09250100 00000400
09250108 00002000
#Software Workaround for errata A-008007 to reset PVR register
09000010 0000000b
09000014 c0000000
09000018 81d00017
89020400 a1000000
091380c0 000f0000
89020400 00000000
#Initialize CPC1 #Initialize CPC1
09010000 00200400 09010000 00200400
09138000 00000000 09138000 00000000