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spi: cadence-quadspi: Reset CMD_CTRL Reg on cmd r/w completion

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If one leaves the CQSPI_REG_CMDCTRL in an unclean state this may cause
issues in future command reads. This issue came to light when some flash
reads in STIG mode were coming back dirty.

Co-developed-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Dhruva Gole 2023-04-12 16:28:56 +05:30 committed by Jagan Teki
parent 8077d296ad
commit 08b3098ead
1 changed files with 3 additions and 0 deletions
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3
drivers/spi/cadence_qspi_apb.c
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@ -376,6 +376,9 @@ int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg)
if (!cadence_qspi_wait_idle(reg_base)) if (!cadence_qspi_wait_idle(reg_base))
return -EIO; return -EIO;
/* Flush the CMDCTRL reg after the execution */
writel(0, reg_base + CQSPI_REG_CMDCTRL);
return 0; return 0;
} }