* Added support for initializing second PCI bus on 85xx
Patch by Andy Fleming 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
Matthew McClintock
parent
b636aaeb6f
commit
087454609e
2 changed files with 171 additions and 38 deletions
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@ -32,17 +32,75 @@
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#if defined(CONFIG_PCI)
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static struct pci_controller *pci_hose;
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void
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pci_mpc85xx_init(struct pci_controller *hose)
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pci_mpc85xx_init(struct pci_controller *board_hose)
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{
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u16 reg16;
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u32 dev;
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volatile immap_t *immap = (immap_t *)CFG_CCSRBAR;
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volatile ccsr_pcix_t *pcix = &immap->im_pcix;
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volatile ccsr_pcix_t *pcix2 = &immap->im_pcix2;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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struct pci_controller * hose;
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u16 reg16;
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pci_hose = board_hose;
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hose = &pci_hose[0];
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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pci_setup_indirect(hose,
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(CFG_IMMR+0x8000),
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(CFG_IMMR+0x8004));
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/*
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* Hose scan.
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*/
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dev = PCI_BDF(hose->first_busno, 0, 0);
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pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
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reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
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/*
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* Clear non-reserved bits in status register.
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*/
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pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
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if (!(gur->pordevsr & PORDEVSR_PCI)) {
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/* PCI-X init */
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reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
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| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
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pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16);
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}
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pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
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pcix->potear1 = 0x00000000;
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pcix->powbar1 = (CFG_PCI1_MEM_PHYS >> 12) & 0x000fffff;
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pcix->powbear1 = 0x00000000;
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pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
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POWAR_MEM_WRITE | POWAR_MEM_512M);
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pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
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pcix->potear2 = 0x00000000;
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pcix->powbar2 = (CFG_PCI1_IO_PHYS >> 12) & 0x000fffff;
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pcix->powbear2 = 0x00000000;
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pcix->powar2 = (POWAR_EN | POWAR_IO_READ |
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POWAR_IO_WRITE | POWAR_IO_1M);
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pcix->pitar1 = 0x00000000;
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pcix->piwbar1 = 0x00000000;
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pcix->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
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PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
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pcix->powar3 = 0;
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pcix->powar4 = 0;
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pcix->piwar2 = 0;
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pcix->piwar3 = 0;
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pci_set_region(hose->regions + 0,
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CFG_PCI1_MEM_BASE,
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CFG_PCI1_MEM_PHYS,
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@ -57,42 +115,8 @@ pci_mpc85xx_init(struct pci_controller *hose)
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hose->region_count = 2;
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pci_setup_indirect(hose,
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(CFG_IMMR+0x8000),
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(CFG_IMMR+0x8004));
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pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
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pcix->potear1 = 0x00000000;
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pcix->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
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pcix->powbear1 = 0x00000000;
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pcix->powar1 = 0x8004401c; /* 512M MEM space */
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pcix->potar2 = 0x00000000;
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pcix->potear2 = 0x00000000;
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pcix->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
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pcix->powbear2 = 0x00000000;
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pcix->powar2 = 0x80088017; /* 16M IO space */
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pcix->pitar1 = 0x00000000;
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pcix->piwbar1 = 0x00000000;
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pcix->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local Mem,
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* Snoop R/W, 2G */
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/*
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* Hose scan.
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*/
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pci_register_hose(hose);
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pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16);
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reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
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/*
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* Clear non-reserved bits in status register.
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*/
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pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
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pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
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#if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS)
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/*
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* This is a SW workaround for an apparent HW problem
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@ -117,6 +141,94 @@ pci_mpc85xx_init(struct pci_controller *hose)
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#endif
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hose->last_busno = pci_hose_scan(hose);
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#ifdef CONFIG_MPC85XX_PCI2
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hose = &pci_hose[1];
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hose->first_busno = pci_hose[0].last_busno + 1;
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hose->last_busno = 0xff;
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pci_setup_indirect(hose,
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(CFG_IMMR+0x9000),
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(CFG_IMMR+0x9004));
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dev = PCI_BDF(hose->first_busno, 0, 0);
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pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
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reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
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/*
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* Clear non-reserved bits in status register.
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*/
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pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
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pcix2->potar1 = (CFG_PCI2_MEM_BASE >> 12) & 0x000fffff;
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pcix2->potear1 = 0x00000000;
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pcix2->powbar1 = (CFG_PCI2_MEM_PHYS >> 12) & 0x000fffff;
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pcix2->powbear1 = 0x00000000;
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pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ |
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POWAR_MEM_WRITE | POWAR_MEM_512M);
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pcix2->potar2 = (CFG_PCI2_IO_BASE >> 12) & 0x000fffff;
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pcix2->potear2 = 0x00000000;
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pcix2->powbar2 = (CFG_PCI2_IO_PHYS >> 12) & 0x000fffff;
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pcix2->powbear2 = 0x00000000;
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pcix2->powar2 = (POWAR_EN | POWAR_IO_READ |
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POWAR_IO_WRITE | POWAR_IO_1M);
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pcix2->pitar1 = 0x00000000;
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pcix2->piwbar1 = 0x00000000;
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pcix2->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
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PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
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pcix2->powar3 = 0;
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pcix2->powar4 = 0;
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pcix2->piwar2 = 0;
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pcix2->piwar3 = 0;
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pci_set_region(hose->regions + 0,
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CFG_PCI2_MEM_BASE,
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CFG_PCI2_MEM_PHYS,
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CFG_PCI2_MEM_SIZE,
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PCI_REGION_MEM);
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pci_set_region(hose->regions + 1,
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CFG_PCI2_IO_BASE,
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CFG_PCI2_IO_PHYS,
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CFG_PCI2_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 2;
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/*
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* Hose scan.
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*/
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pci_register_hose(hose);
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hose->last_busno = pci_hose_scan(hose);
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#endif
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}
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#ifdef CONFIG_OF_FLAT_TREE
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void
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ft_pci_setup(void *blob, bd_t *bd)
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{
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u32 *p;
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int len;
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p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
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if (p != NULL) {
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p[0] = pci_hose[0].first_busno;
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p[1] = pci_hose[0].last_busno;
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}
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#ifdef CONFIG_MPC85XX_PCI2
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p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@9000/bus-range", &len);
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if (p != NULL) {
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p[0] = pci_hose[1].first_busno;
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p[1] = pci_hose[1].last_busno;
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}
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#endif
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}
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#endif /* CONFIG_OF_FLAT_TREE */
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#endif /* CONFIG_PCI */
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@ -246,7 +246,6 @@ typedef struct ccsr_lbc {
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/*
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* PCI Registers(0x8000-0x9000)
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* Omitting Reserved(0x9000-0x2_0000)
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*/
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typedef struct ccsr_pcix {
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uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */
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@ -309,9 +308,27 @@ typedef struct ccsr_pcix {
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uint peextaddrcr; /* 0x8e14 - PCIX Error Extended Address Capture Register */
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uint pedlcr; /* 0x8e18 - PCIX Error Data Low Capture Register */
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uint pedhcr; /* 0x8e1c - PCIX Error Error Data High Capture Register */
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char res11[94688];
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uint gas_timr; /* 0x8e20 - PCIX Gasket Timer Register */
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char res11[476];
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} ccsr_pcix_t;
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#define PCIX_COMMAND 0x62
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#define POWAR_EN 0x80000000
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#define POWAR_IO_READ 0x00080000
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#define POWAR_MEM_READ 0x00040000
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#define POWAR_IO_WRITE 0x00008000
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#define POWAR_MEM_WRITE 0x00004000
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#define POWAR_MEM_512M 0x0000001c
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#define POWAR_IO_1M 0x00000013
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#define PIWAR_EN 0x80000000
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#define PIWAR_PF 0x20000000
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#define PIWAR_LOCAL 0x00f00000
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#define PIWAR_READ_SNOOP 0x00050000
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#define PIWAR_WRITE_SNOOP 0x00005000
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#define PIWAR_MEM_2G 0x0000001e
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/*
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* L2 Cache Registers(0x2_0000-0x2_1000)
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*/
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@ -1572,6 +1589,8 @@ typedef struct ccsr_gur {
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char res15[61651];
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} ccsr_gur_t;
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#define PORDEVSR_PCI (0x00800000) /* PCI Mode */
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typedef struct immap {
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ccsr_local_ecm_t im_local_ecm;
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ccsr_ddr_t im_ddr;
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@ -1579,6 +1598,8 @@ typedef struct immap {
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ccsr_duart_t im_duart;
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ccsr_lbc_t im_lbc;
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ccsr_pcix_t im_pcix;
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ccsr_pcix_t im_pcix2;
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char reserved[90112];
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ccsr_l2cache_t im_l2cache;
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ccsr_dma_t im_dma;
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ccsr_tsec_t im_tsec1;
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