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armv8/fsl-lsch3: Set nodes in DVM domain

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This is required for TLB invalidation broadcasts to work.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Scott Wood 2015-03-20 19:28:10 -07:00 committed by York Sun
parent 05d2e21be5
commit 07c6600068
2 changed files with 15 additions and 0 deletions
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9
arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
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@ -15,6 +15,15 @@
ENTRY(lowlevel_init)
mov x29, lr /* Save LR */
/* Add fully-coherent masters to DVM domain */
ldr x1, =CCI_MN_BASE
ldr x2, [x1, #CCI_MN_RNF_NODEID_LIST]
str x2, [x1, #CCI_MN_DVM_DOMAIN_CTL_SET]
1: ldr x3, [x1, #CCI_MN_DVM_DOMAIN_CTL_SET]
mvn x0, x3
tst x0, x3 /* Wait for domain addition to complete */
b.ne 1b
/* Set the SMMU page size in the sACR register */
ldr x1, =SMMU_BASE
ldr w0, [x1, #0x10]

6
arch/arm/include/asm/arch-fsl-lsch3/config.h
View file

@ -118,6 +118,12 @@
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
/* Cache Coherent Interconnect */
#define CCI_MN_BASE 0x04000000
#define CCI_MN_RNF_NODEID_LIST 0x180
#define CCI_MN_DVM_DOMAIN_CTL 0x200
#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
#ifdef CONFIG_LS2085A
#define CONFIG_MAX_CPUS 16
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8