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arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode

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While we setup the mmu initially we mark set_section_dcache with
DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro
is rightly defined with TTB_SECT_XN_MASK set so as to mark all the
4GB XN. In case of LPAE mode  XN(Execute-never) bit is not set with
DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which
keeps all the regions execute okay and this leads to random speculative
fetches in random memory regions which was eventually caught by kernel
omap-l3-noc driver.

Fix this to mark the regions as XN by default.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Keerthy 2016-10-29 15:19:10 +05:30 committed by Tom Rini
parent 2b373cb83c
commit 06d43c808d
2 changed files with 6 additions and 1 deletions
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2
arch/arm/include/asm/system.h
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@ -331,7 +331,7 @@ static inline void set_dacr(unsigned int val)
/* options available for data cache on each page */
enum dcache_option {
DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0),
DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0) | TTB_SECT_XN_MASK,
DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1),
DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2),
DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3),

5
arch/arm/lib/cache-cp15.c
View file

@ -71,8 +71,13 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
start = start >> MMU_SECTION_SHIFT;
#ifdef CONFIG_ARMV7_LPAE
debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size,
option);
#else
debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
option);
#endif
for (upto = start; upto < end; upto++)
set_section_dcache(upto, option);