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powerpc/t2080: updating rcw for silicon v1.1

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T2080 v1.1 requires different MEM_PLL_RAT from previous v1.0,
and also update core frequency to 1.8GHz for v1.1.
We reserve the support for T2080 v1.0 and enable v1.1 by default.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Shengzhou Liu 2014-11-14 10:31:22 +08:00 committed by York Sun
parent e2544e7a54
commit 06b3acf184
2 changed files with 26 additions and 10 deletions
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16
board/freescale/t208xqds/t2080_rcw.cfg
View file

@ -1,8 +1,16 @@
#PBL preamble and RCW header
aa55aa55 010e0100
#SerDes Protocol: 0x66_0x16
#Core/DDR: 1533Mhz/2133MT/s
12100017 15000000 00000000 00000000
66150002 00008400 e8104000 c1000000
#For T2080 v1.0
#SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s
#12100017 15000000 00000000 00000000
#66150002 00008400 e8104000 c1000000
#00000000 00000000 00000000 000307fc
#00000000 00000000 00000000 00000004
#For T2080 v1.1
#SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s
0c070012 0e000000 00000000 00000000
66150002 00000000 e8104000 c1000000
00000000 00000000 00000000 000307fc
00000000 00000000 00000000 00000004

20
board/freescale/t208xrdb/t2080_rcw.cfg
View file

@ -1,8 +1,16 @@
#PBL preamble and RCW header for T2080RDB
#PBL preamble and RCW header
aa55aa55 010e0100
#SerDes Protocol: 0x66_0x16
#Core/DDR: 1533Mhz/1600MT/s
120c0017 15000000 00000000 00000000
66150002 00008400 ec104000 c1000000
00000000 00000000 00000000 000307fc
#For T2080 v1.0
#SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
#120c0017 15000000 00000000 00000000
#66150002 00008400 ec104000 c1000000
#00000000 00000000 00000000 000307fc
#00000000 00000000 00000000 00000004
#For T2080 v1.1
#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
1206001b 15000000 00000000 00000000
66150002 00000000 e8104000 c1000000
00800000 00000000 00000000 000307fc
00000000 00000000 00000000 00000004