imx: update i.MX8MQ device trees
This updates the i.MX8MQ device trees and, necessarily, also the i.MX8MQ clock bindings. These are taken verbatim from from the Linux kernel version v5.4-rc2, which three small changes which were already part of the previous device tree: * Keep the PSCI reserved memory range * Keep the alias for ethernet, so that the MAC address can be set * Keep the modified #include for the IOMUXC pins Signed-off-by: Patrick Wildt <patrick@blueri.se> Acked-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Patrick Wildt
Stefano Babic
parent
c4cb27e59f
commit
05737f3585
8 changed files with 1776 additions and 1259 deletions
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@ -656,8 +656,9 @@ dtb-$(CONFIG_ARCH_IMX8) += \
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fsl-imx8qxp-colibri.dtb \
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fsl-imx8qxp-mek.dtb
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dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb \
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imx8mm-evk.dtb
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dtb-$(CONFIG_ARCH_IMX8M) += \
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imx8mm-evk.dtb \
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imx8mq-evk.dtb
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dtb-$(CONFIG_RCAR_GEN2) += \
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r8a7790-lager-u-boot.dtb \
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@ -1,414 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP
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*/
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/dts-v1/;
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/* First 128KB is for PSCI ATF. */
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/memreserve/ 0x40000000 0x00020000;
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#include "fsl-imx8mq.dtsi"
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/ {
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model = "Freescale i.MX8MQ EVK";
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compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
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chosen {
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bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_usdhc2_vmmc: usdhc2_vmmc {
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compatible = "regulator-fixed";
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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pwmleds {
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compatible = "pwm-leds";
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ledpwm2 {
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label = "PWM2";
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pwms = <&pwm2 0 50000>;
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max-brightness = <255>;
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};
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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imx8mq-evk {
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
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MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
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MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
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MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
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MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
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MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
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MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
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MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
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MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
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MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
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MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
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MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
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MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
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MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
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MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
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MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
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MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
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>;
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};
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pinctrl_pwm2: pwm2grp {
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fsl,pins = <
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MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16
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>;
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};
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pinctrl_qspi: qspigrp {
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fsl,pins = <
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MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
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MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
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MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
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MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
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MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
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MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
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MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
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MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
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MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
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MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
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MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
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MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
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MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
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MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
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MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
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MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
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MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
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>;
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};
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pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
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fsl,pins = <
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MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
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MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
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MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
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MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
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MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
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MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
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MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
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MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
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MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
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MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
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MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
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MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
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>;
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};
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pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
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fsl,pins = <
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MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
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MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
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MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
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MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
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MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
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MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
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MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
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MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
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MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
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MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
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MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
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MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
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>;
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};
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pinctrl_usdhc2_gpio: usdhc2grpgpio {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
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MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
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MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
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MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
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MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
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MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
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MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
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MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
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MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
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MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
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MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
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MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
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MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
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MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
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MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
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MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
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MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
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MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
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MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
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MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
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>;
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};
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pinctrl_sai2: sai2grp {
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fsl,pins = <
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MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
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MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
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MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
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MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
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MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
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>;
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};
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pinctrl_wdog: wdoggrp {
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fsl,pins = <
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MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
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>;
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};
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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at803x,led-act-blind-workaround;
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at803x,eee-disabled;
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};
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};
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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pmic: pfuze100@08 {
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compatible = "fsl,pfuze100";
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reg = <0x08>;
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regulators {
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sw1a_reg: sw1ab {
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regulator-min-microvolt = <300000>;
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regulator-max-microvolt = <1875000>;
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regulator-always-on;
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};
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sw1c_reg: sw1c {
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regulator-min-microvolt = <300000>;
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regulator-max-microvolt = <1875000>;
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regulator-always-on;
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};
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sw2_reg: sw2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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sw3a_reg: sw3ab {
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regulator-min-microvolt = <400000>;
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regulator-max-microvolt = <1975000>;
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regulator-always-on;
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};
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sw4_reg: sw4 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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swbst_reg: swbst {
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5150000>;
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};
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snvs_reg: vsnvs {
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <3000000>;
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regulator-always-on;
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};
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vref_reg: vrefddr {
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regulator-always-on;
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};
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vgen1_reg: vgen1 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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};
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vgen2_reg: vgen2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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regulator-always-on;
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};
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vgen3_reg: vgen3 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen4_reg: vgen4 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen5_reg: vgen5 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen6_reg: vgen6 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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};
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};
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&i2c2 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "disabled";
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};
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&pwm2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm2>;
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status = "okay";
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};
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&lcdif {
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status = "okay";
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disp-dev = "mipi_dsi_northwest";
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display = <&display0>;
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display0: display@0 {
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bits-per-pixel = <24>;
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bus-width = <24>;
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display-timings {
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native-mode = <&timing0>;
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timing0: timing0 {
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clock-frequency = <9200000>;
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hactive = <480>;
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vactive = <272>;
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hfront-porch = <8>;
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hback-porch = <4>;
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hsync-len = <41>;
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vback-porch = <2>;
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vfront-porch = <4>;
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vsync-len = <10>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <1>;
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pixelclk-active = <0>;
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};
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};
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};
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};
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&qspi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_qspi>;
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status = "okay";
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flash0: n25q256a@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "micron,n25q256a";
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spi-max-frequency = <29000000>;
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spi-nor,ddr-quad-read-dummy = <6>;
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};
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};
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&usdhc2 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
|
||||
vmmc-supply = <®_usdhc2_vmmc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -1,462 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "fsl-imx8-ca53.dtsi"
|
||||
#include <dt-bindings/clock/imx8mq-clock.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/pinctrl/pins-imx8mq.h>
|
||||
#include <dt-bindings/reset/imx8mq-reset.h>
|
||||
#include <dt-bindings/power/imx8mq-power.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
/ {
|
||||
compatible = "fsl,imx8mq";
|
||||
interrupt-parent = <&gpc>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &fec1;
|
||||
mmc0 = &usdhc1;
|
||||
mmc1 = &usdhc2;
|
||||
gpio0 = &gpio1;
|
||||
gpio1 = &gpio2;
|
||||
gpio2 = &gpio3;
|
||||
gpio3 = &gpio4;
|
||||
gpio4 = &gpio5;
|
||||
i2c0 = &i2c1;
|
||||
i2c1 = &i2c2;
|
||||
i2c2 = &i2c3;
|
||||
i2c3 = &i2c4;
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x40000000 0 0xc0000000>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@38800000 {
|
||||
compatible = "arm,gic-v3";
|
||||
reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
|
||||
<0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&gic>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) |
|
||||
IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) |
|
||||
IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) |
|
||||
IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) |
|
||||
IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
|
||||
clock-frequency = <8333333>;
|
||||
interrupt-parent = <&gic>;
|
||||
};
|
||||
|
||||
pwm2: pwm@30670000 {
|
||||
compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x0 0x30670000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
|
||||
<&clk IMX8MQ_CLK_PWM2_ROOT>;
|
||||
clock-names = "ipg", "per";
|
||||
#pwm-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio1: gpio@30200000 {
|
||||
compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x0 0x30200000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@30210000 {
|
||||
compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x0 0x30210000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@30220000 {
|
||||
compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x0 0x30220000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio4: gpio@30230000 {
|
||||
compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x0 0x30230000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio5: gpio@30240000 {
|
||||
compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x0 0x30240000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
tmu: tmu@30260000 {
|
||||
compatible = "fsl,imx8mq-tmu";
|
||||
reg = <0x0 0x30260000 0x0 0x10000>;
|
||||
interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
little-endian;
|
||||
u-boot,dm-pre-reloc;
|
||||
fsl,tmu-range = <0xa0000 0x90026 0x8004a 0x1006a>;
|
||||
fsl,tmu-calibration = <0x00000000 0x00000020
|
||||
0x00000001 0x00000028
|
||||
0x00000002 0x00000030
|
||||
0x00000003 0x00000038
|
||||
0x00000004 0x00000040
|
||||
0x00000005 0x00000048
|
||||
0x00000006 0x00000050
|
||||
0x00000007 0x00000058
|
||||
0x00000008 0x00000060
|
||||
0x00000009 0x00000068
|
||||
0x0000000a 0x00000070
|
||||
0x0000000b 0x00000077
|
||||
|
||||
0x00010000 0x00000057
|
||||
0x00010001 0x0000005b
|
||||
0x00010002 0x0000005f
|
||||
0x00010003 0x00000063
|
||||
0x00010004 0x00000067
|
||||
0x00010005 0x0000006b
|
||||
0x00010006 0x0000006f
|
||||
0x00010007 0x00000073
|
||||
0x00010008 0x00000077
|
||||
0x00010009 0x0000007b
|
||||
0x0001000a 0x0000007f
|
||||
|
||||
0x00020000 0x00000002
|
||||
0x00020001 0x0000000e
|
||||
0x00020002 0x0000001a
|
||||
0x00020003 0x00000026
|
||||
0x00020004 0x00000032
|
||||
0x00020005 0x0000003e
|
||||
0x00020006 0x0000004a
|
||||
0x00020007 0x00000056
|
||||
0x00020008 0x00000062
|
||||
|
||||
0x00030000 0x00000000
|
||||
0x00030001 0x00000008
|
||||
0x00030002 0x00000010
|
||||
0x00030003 0x00000018
|
||||
0x00030004 0x00000020
|
||||
0x00030005 0x00000028
|
||||
0x00030006 0x00000030
|
||||
0x00030007 0x00000038>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
/* cpu thermal */
|
||||
cpu-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <2000>;
|
||||
thermal-sensors = <&tmu>;
|
||||
trips {
|
||||
cpu_alert0: trip0 {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
cpu_crit0: trip1 {
|
||||
temperature = <125000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu_alert0>;
|
||||
cooling-device =
|
||||
<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lcdif: lcdif@30320000 {
|
||||
compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
|
||||
reg = <0x0 0x30320000 0x0 0x10000>;
|
||||
clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_DIV>,
|
||||
<&clk IMX8MQ_CLK_DUMMY>,
|
||||
<&clk IMX8MQ_CLK_DUMMY>;
|
||||
clock-names = "pix", "axi", "disp_axi";
|
||||
assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_SRC>;
|
||||
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
|
||||
assigned-clock-rate = <594000000>;
|
||||
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
iomuxc: iomuxc@30330000 {
|
||||
compatible = "fsl,imx8mq-iomuxc";
|
||||
reg = <0x0 0x30330000 0x0 0x10000>;
|
||||
};
|
||||
|
||||
gpr: iomuxc-gpr@30340000 {
|
||||
compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx7d-iomuxc-gpr", "syscon";
|
||||
reg = <0x0 0x30340000 0x0 0x10000>;
|
||||
};
|
||||
|
||||
ocotp: ocotp-ctrl@30350000 {
|
||||
compatible = "fsl,imx8mq-ocotp", "fsl,imx7d-ocotp", "syscon";
|
||||
reg = <0x0 0x30350000 0x0 0x10000>;
|
||||
};
|
||||
|
||||
anatop: anatop@30360000 {
|
||||
compatible = "fsl,imx8mq-anatop", "fsl,imx6q-anatop",
|
||||
"syscon", "simple-bus";
|
||||
reg = <0x0 0x30360000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
clk: ccm@30380000 {
|
||||
compatible = "fsl,imx8mq-ccm";
|
||||
reg = <0x0 0x30380000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
src: reset-controller@30390000 {
|
||||
compatible = "fsl,imx8mq-src", "syscon";
|
||||
reg = <0x0 0x30390000 0x0 0x10000>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
gpc: gpc@303a0000 {
|
||||
compatible = "fsl,imx8mq-gpc", "fsl,imx7d-gpc", "syscon";
|
||||
reg = <0x0 0x303a0000 0x0 0x10000>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
pgc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/*
|
||||
* As per comment in ATF source code:
|
||||
*
|
||||
* PCIE1 and PCIE2 share the
|
||||
* same reset signal, if we
|
||||
* power down PCIE2, PCIE1
|
||||
* will be held in reset too.
|
||||
*
|
||||
* So instead of creating two
|
||||
* separate power domains for
|
||||
* PCIE1 and PCIE2 we create a
|
||||
* link between both and use
|
||||
* it as a shared PCIE power
|
||||
* domain.
|
||||
*/
|
||||
pgc_pcie: power-domain@1 {
|
||||
#power-domain-cells = <0>;
|
||||
reg = <IMX8M_POWER_DOMAIN_PCIE1>;
|
||||
power-domains = <&pgc_pcie2>;
|
||||
};
|
||||
|
||||
pgc_pcie2: power-domain@a {
|
||||
#power-domain-cells = <0>;
|
||||
reg = <IMX8M_POWER_DOMAIN_PCIE2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usdhc1: usdhc@30b40000 {
|
||||
compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
|
||||
reg = <0x0 0x30b40000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_DUMMY>,
|
||||
<&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
|
||||
<&clk IMX8MQ_CLK_USDHC1_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
assigned-clocks = <&clk IMX8MQ_CLK_USDHC1_DIV>;
|
||||
assigned-clock-rates = <400000000>;
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usdhc2: usdhc@30b50000 {
|
||||
compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
|
||||
reg = <0x0 0x30b50000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_DUMMY>,
|
||||
<&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
|
||||
<&clk IMX8MQ_CLK_USDHC2_ROOT>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
fsl,tuning-start-tap = <20>;
|
||||
fsl,tuning-step= <2>;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fec1: ethernet@30be0000 {
|
||||
compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
|
||||
reg = <0x0 0x30be0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
|
||||
<&clk IMX8MQ_CLK_ENET1_ROOT>,
|
||||
<&clk IMX8MQ_CLK_ENET_TIMER_DIV>,
|
||||
<&clk IMX8MQ_CLK_ENET_REF_DIV>,
|
||||
<&clk IMX8MQ_CLK_ENET_PHY_REF_DIV>;
|
||||
clock-names = "ipg", "ahb", "ptp",
|
||||
"enet_clk_ref", "enet_out";
|
||||
assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI_SRC>,
|
||||
<&clk IMX8MQ_CLK_ENET_TIMER_SRC>,
|
||||
<&clk IMX8MQ_CLK_ENET_REF_SRC>,
|
||||
<&clk IMX8MQ_CLK_ENET_TIMER_DIV>;
|
||||
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
|
||||
<&clk IMX8MQ_SYS2_PLL_100M>,
|
||||
<&clk IMX8MQ_SYS2_PLL_125M>;
|
||||
assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
|
||||
stop-mode = <&gpr 0x10 3>;
|
||||
fsl,num-tx-queues=<3>;
|
||||
fsl,num-rx-queues=<3>;
|
||||
fsl,wakeup_irq = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
imx_ion {
|
||||
compatible = "fsl,mxc-ion";
|
||||
fsl,heap-id = <0>;
|
||||
};
|
||||
|
||||
i2c1: i2c@30a20000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx21-i2c";
|
||||
reg = <0x0 0x30a20000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@30a30000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx21-i2c";
|
||||
reg = <0x0 0x30a30000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@30a40000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx21-i2c";
|
||||
reg = <0x0 0x30a40000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@30a50000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx21-i2c";
|
||||
reg = <0x0 0x30a50000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog1: wdog@30280000 {
|
||||
compatible = "fsl,imx21-wdt";
|
||||
reg = <0 0x30280000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog2: wdog@30290000 {
|
||||
compatible = "fsl,imx21-wdt";
|
||||
reg = <0 0x30290000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog3: wdog@302a0000 {
|
||||
compatible = "fsl,imx21-wdt";
|
||||
reg = <0 0x302a0000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dma_cap: dma_cap {
|
||||
compatible = "dma-capability";
|
||||
only-dma-mask32 = <1>;
|
||||
};
|
||||
|
||||
qspi: qspi@30bb0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx7d-qspi";
|
||||
reg = <0 0x30bb0000 0 0x10000>, <0 0x08000000 0 0x10000000>;
|
||||
reg-names = "QuadSPI", "QuadSPI-memory";
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
|
||||
<&clk IMX8MQ_CLK_QSPI_ROOT>;
|
||||
clock-names = "qspi_en", "qspi";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&A53_0 {
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
486
arch/arm/dts/imx8mq-evk.dts
Normal file
486
arch/arm/dts/imx8mq-evk.dts
Normal file
|
|
@ -0,0 +1,486 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright 2017 NXP
|
||||
* Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/* First 128KB is for PSCI ATF. */
|
||||
/memreserve/ 0x40000000 0x00020000;
|
||||
|
||||
#include "imx8mq.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NXP i.MX8MQ EVK";
|
||||
compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart1;
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x40000000 0 0xc0000000>;
|
||||
};
|
||||
|
||||
pcie0_refclk: pcie0-refclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
reg_usdhc2_vmmc: regulator-vsd-3v3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_reg_usdhc2>;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VSD_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
buck2_reg: regulator-buck2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_buck2>;
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "vdd_arm";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
|
||||
states = <1000000 0x0
|
||||
900000 0x1>;
|
||||
};
|
||||
|
||||
wm8524: audio-codec {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "wlf,wm8524";
|
||||
wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
sound-wm8524 {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "wm8524-audio";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,frame-master = <&cpudai>;
|
||||
simple-audio-card,bitclock-master = <&cpudai>;
|
||||
simple-audio-card,widgets =
|
||||
"Line", "Left Line Out Jack",
|
||||
"Line", "Right Line Out Jack";
|
||||
simple-audio-card,routing =
|
||||
"Left Line Out Jack", "LINEVOUTL",
|
||||
"Right Line Out Jack", "LINEVOUTR";
|
||||
|
||||
cpudai: simple-audio-card,cpu {
|
||||
sound-dai = <&sai2>;
|
||||
};
|
||||
|
||||
link_codec: simple-audio-card,codec {
|
||||
sound-dai = <&wm8524>;
|
||||
clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&A53_0 {
|
||||
cpu-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
&A53_1 {
|
||||
cpu-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
&A53_2 {
|
||||
cpu-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
&A53_3 {
|
||||
cpu-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec1>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy0>;
|
||||
fsl,magic-packet;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sai2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sai2>;
|
||||
assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>;
|
||||
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>;
|
||||
assigned-clock-rates = <0>, <24576000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio5 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wifi_reset>;
|
||||
|
||||
wl-reg-on {
|
||||
gpio-hog;
|
||||
gpios = <29 GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
|
||||
pmic@8 {
|
||||
compatible = "fsl,pfuze100";
|
||||
reg = <0x8>;
|
||||
|
||||
regulators {
|
||||
sw1a_reg: sw1ab {
|
||||
regulator-min-microvolt = <825000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
};
|
||||
|
||||
sw1c_reg: sw1c {
|
||||
regulator-min-microvolt = <825000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
};
|
||||
|
||||
sw2_reg: sw2 {
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw3a_reg: sw3ab {
|
||||
regulator-min-microvolt = <825000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw4_reg: sw4 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
swbst_reg: swbst {
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5150000>;
|
||||
};
|
||||
|
||||
snvs_reg: vsnvs {
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vref_reg: vrefddr {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen1_reg: vgen1 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
};
|
||||
|
||||
vgen2_reg: vgen2 {
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <975000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen3_reg: vgen3 {
|
||||
regulator-min-microvolt = <1675000>;
|
||||
regulator-max-microvolt = <1975000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen4_reg: vgen4 {
|
||||
regulator-min-microvolt = <1625000>;
|
||||
regulator-max-microvolt = <1875000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen5_reg: vgen5 {
|
||||
regulator-min-microvolt = <3075000>;
|
||||
regulator-max-microvolt = <3625000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen6_reg: vgen6 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcie0>;
|
||||
reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
|
||||
clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
|
||||
<&clk IMX8MQ_CLK_PCIE1_AUX>,
|
||||
<&clk IMX8MQ_CLK_PCIE1_PHY>,
|
||||
<&pcie0_refclk>;
|
||||
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pgc_gpu {
|
||||
power-supply = <&sw1a_reg>;
|
||||
};
|
||||
|
||||
&snvs_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_dwc3_1 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_qspi>;
|
||||
status = "okay";
|
||||
|
||||
n25q256a: flash@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "micron,n25q256a", "jedec,spi-nor";
|
||||
spi-max-frequency = <29000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
|
||||
vqmmc-supply = <&sw4_reg>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
|
||||
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
|
||||
vmmc-supply = <®_usdhc2_vmmc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_buck2: vddarmgrp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
|
||||
>;
|
||||
|
||||
};
|
||||
|
||||
pinctrl_fec1: fec1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
|
||||
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
|
||||
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
|
||||
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
|
||||
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
|
||||
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
|
||||
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
|
||||
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
|
||||
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
|
||||
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
|
||||
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
|
||||
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
|
||||
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
|
||||
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
|
||||
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
|
||||
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcie0: pcie0grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76
|
||||
MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_qspi: qspigrp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
|
||||
MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
|
||||
MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
|
||||
MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
|
||||
MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
|
||||
MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
|
||||
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_reg_usdhc2: regusdhc2grpgpio {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sai2: sai2grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
|
||||
MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
|
||||
MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
|
||||
MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
|
||||
MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
|
||||
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
|
||||
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
|
||||
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
|
||||
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
|
||||
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_100mhz: usdhc1-100grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
|
||||
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
|
||||
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
|
||||
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
|
||||
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1-200grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
|
||||
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
|
||||
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
|
||||
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
|
||||
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
|
||||
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
|
||||
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
|
||||
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
|
||||
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
|
||||
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
|
||||
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2-100grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
|
||||
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
|
||||
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
|
||||
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
|
||||
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
|
||||
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
|
||||
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2-200grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
|
||||
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
|
||||
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
|
||||
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
|
||||
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
|
||||
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
|
||||
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdog1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wifi_reset: wifiresetgrp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16
|
||||
>;
|
||||
};
|
||||
};
|
||||
1111
arch/arm/dts/imx8mq.dtsi
Normal file
1111
arch/arm/dts/imx8mq.dtsi
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -25,7 +25,7 @@ CONFIG_CMD_EXT4=y
|
|||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-evk"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx8mq-evk"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
|
||||
CONFIG_DM_GPIO=y
|
||||
|
|
|
|||
|
|
@ -107,7 +107,7 @@
|
|||
"fdt_addr=0x43000000\0" \
|
||||
"fdt_high=0xffffffffffffffff\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"fdt_file=fsl-imx8mq-evk.dtb\0" \
|
||||
"fdt_file=imx8mq-evk.dtb\0" \
|
||||
"initrd_addr=0x43800000\0" \
|
||||
"initrd_high=0xffffffffffffffff\0" \
|
||||
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
|
||||
|
|
|
|||
|
|
@ -1,10 +1,7 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H
|
||||
|
|
@ -148,465 +145,263 @@
|
|||
|
||||
/* BUS TYPE */
|
||||
/* MAIN AXI */
|
||||
#define IMX8MQ_CLK_MAIN_AXI_SRC 103
|
||||
#define IMX8MQ_CLK_MAIN_AXI_CG 104
|
||||
#define IMX8MQ_CLK_MAIN_AXI_PRE_DIV 105
|
||||
#define IMX8MQ_CLK_MAIN_AXI_DIV 106
|
||||
#define IMX8MQ_CLK_MAIN_AXI 103
|
||||
/* ENET AXI */
|
||||
#define IMX8MQ_CLK_ENET_AXI_SRC 107
|
||||
#define IMX8MQ_CLK_ENET_AXI_CG 108
|
||||
#define IMX8MQ_CLK_ENET_AXI_PRE_DIV 109
|
||||
#define IMX8MQ_CLK_ENET_AXI_DIV 110
|
||||
#define IMX8MQ_CLK_ENET_AXI 104
|
||||
/* NAND_USDHC_BUS */
|
||||
#define IMX8MQ_CLK_NAND_USDHC_BUS_SRC 111
|
||||
#define IMX8MQ_CLK_NAND_USDHC_BUS_CG 112
|
||||
#define IMX8MQ_CLK_NAND_USDHC_BUS_PRE_DIV 113
|
||||
#define IMX8MQ_CLK_NAND_USDHC_BUS_DIV 114
|
||||
#define IMX8MQ_CLK_NAND_USDHC_BUS 105
|
||||
/* VPU BUS */
|
||||
#define IMX8MQ_CLK_VPU_BUS_SRC 115
|
||||
#define IMX8MQ_CLK_VPU_BUS_CG 116
|
||||
#define IMX8MQ_CLK_VPU_BUS_PRE_DIV 117
|
||||
#define IMX8MQ_CLK_VPU_BUS_DIV 118
|
||||
#define IMX8MQ_CLK_VPU_BUS 106
|
||||
/* DISP_AXI */
|
||||
#define IMX8MQ_CLK_DISP_AXI_SRC 119
|
||||
#define IMX8MQ_CLK_DISP_AXI_CG 120
|
||||
#define IMX8MQ_CLK_DISP_AXI_PRE_DIV 121
|
||||
#define IMX8MQ_CLK_DISP_AXI_DIV 122
|
||||
#define IMX8MQ_CLK_DISP_AXI 107
|
||||
/* DISP APB */
|
||||
#define IMX8MQ_CLK_DISP_APB_SRC 123
|
||||
#define IMX8MQ_CLK_DISP_APB_CG 124
|
||||
#define IMX8MQ_CLK_DISP_APB_PRE_DIV 125
|
||||
#define IMX8MQ_CLK_DISP_APB_DIV 126
|
||||
#define IMX8MQ_CLK_DISP_APB 108
|
||||
/* DISP RTRM */
|
||||
#define IMX8MQ_CLK_DISP_RTRM_SRC 127
|
||||
#define IMX8MQ_CLK_DISP_RTRM_CG 128
|
||||
#define IMX8MQ_CLK_DISP_RTRM_PRE_DIV 129
|
||||
#define IMX8MQ_CLK_DISP_RTRM_DIV 130
|
||||
#define IMX8MQ_CLK_DISP_RTRM 109
|
||||
/* USB_BUS */
|
||||
#define IMX8MQ_CLK_USB_BUS_SRC 131
|
||||
#define IMX8MQ_CLK_USB_BUS_CG 132
|
||||
#define IMX8MQ_CLK_USB_BUS_PRE_DIV 133
|
||||
#define IMX8MQ_CLK_USB_BUS_DIV 134
|
||||
#define IMX8MQ_CLK_USB_BUS 110
|
||||
/* GPU_AXI */
|
||||
#define IMX8MQ_CLK_GPU_AXI_SRC 135
|
||||
#define IMX8MQ_CLK_GPU_AXI_CG 136
|
||||
#define IMX8MQ_CLK_GPU_AXI_PRE_DIV 137
|
||||
#define IMX8MQ_CLK_GPU_AXI_DIV 138
|
||||
#define IMX8MQ_CLK_GPU_AXI 111
|
||||
/* GPU_AHB */
|
||||
#define IMX8MQ_CLK_GPU_AHB_SRC 139
|
||||
#define IMX8MQ_CLK_GPU_AHB_CG 140
|
||||
#define IMX8MQ_CLK_GPU_AHB_PRE_DIV 141
|
||||
#define IMX8MQ_CLK_GPU_AHB_DIV 142
|
||||
#define IMX8MQ_CLK_GPU_AHB 112
|
||||
/* NOC */
|
||||
#define IMX8MQ_CLK_NOC_SRC 143
|
||||
#define IMX8MQ_CLK_NOC_CG 144
|
||||
#define IMX8MQ_CLK_NOC_PRE_DIV 145
|
||||
#define IMX8MQ_CLK_NOC_DIV 146
|
||||
#define IMX8MQ_CLK_NOC 113
|
||||
/* NOC_APB */
|
||||
#define IMX8MQ_CLK_NOC_APB_SRC 147
|
||||
#define IMX8MQ_CLK_NOC_APB_CG 148
|
||||
#define IMX8MQ_CLK_NOC_APB_PRE_DIV 149
|
||||
#define IMX8MQ_CLK_NOC_APB_DIV 150
|
||||
#define IMX8MQ_CLK_NOC_APB 115
|
||||
|
||||
/* AHB */
|
||||
#define IMX8MQ_CLK_AHB_SRC 151
|
||||
#define IMX8MQ_CLK_AHB_CG 152
|
||||
#define IMX8MQ_CLK_AHB_PRE_DIV 153
|
||||
#define IMX8MQ_CLK_AHB_DIV 154
|
||||
#define IMX8MQ_CLK_AHB 116
|
||||
/* AUDIO AHB */
|
||||
#define IMX8MQ_CLK_AUDIO_AHB_SRC 155
|
||||
#define IMX8MQ_CLK_AUDIO_AHB_CG 156
|
||||
#define IMX8MQ_CLK_AUDIO_AHB_PRE_DIV 157
|
||||
#define IMX8MQ_CLK_AUDIO_AHB_DIV 158
|
||||
#define IMX8MQ_CLK_AUDIO_AHB 117
|
||||
|
||||
/* DRAM_ALT */
|
||||
#define IMX8MQ_CLK_DRAM_ALT_SRC 159
|
||||
#define IMX8MQ_CLK_DRAM_ALT_CG 160
|
||||
#define IMX8MQ_CLK_DRAM_ALT_PRE_DIV 161
|
||||
#define IMX8MQ_CLK_DRAM_ALT_DIV 162
|
||||
#define IMX8MQ_CLK_DRAM_ALT 118
|
||||
/* DRAM APB */
|
||||
#define IMX8MQ_CLK_DRAM_APB_SRC 163
|
||||
#define IMX8MQ_CLK_DRAM_APB_CG 164
|
||||
#define IMX8MQ_CLK_DRAM_APB_PRE_DIV 165
|
||||
#define IMX8MQ_CLK_DRAM_APB_DIV 166
|
||||
#define IMX8MQ_CLK_DRAM_APB 119
|
||||
/* VPU_G1 */
|
||||
#define IMX8MQ_CLK_VPU_G1_SRC 167
|
||||
#define IMX8MQ_CLK_VPU_G1_CG 168
|
||||
#define IMX8MQ_CLK_VPU_G1_PRE_DIV 169
|
||||
#define IMX8MQ_CLK_VPU_G1_DIV 170
|
||||
#define IMX8MQ_CLK_VPU_G1 120
|
||||
/* VPU_G2 */
|
||||
#define IMX8MQ_CLK_VPU_G2_SRC 171
|
||||
#define IMX8MQ_CLK_VPU_G2_CG 172
|
||||
#define IMX8MQ_CLK_VPU_G2_PRE_DIV 173
|
||||
#define IMX8MQ_CLK_VPU_G2_DIV 174
|
||||
#define IMX8MQ_CLK_VPU_G2 121
|
||||
/* DISP_DTRC */
|
||||
#define IMX8MQ_CLK_DISP_DTRC_SRC 175
|
||||
#define IMX8MQ_CLK_DISP_DTRC_CG 176
|
||||
#define IMX8MQ_CLK_DISP_DTRC_PRE_DIV 177
|
||||
#define IMX8MQ_CLK_DISP_DTRC_DIV 178
|
||||
#define IMX8MQ_CLK_DISP_DTRC 122
|
||||
/* DISP_DC8000 */
|
||||
#define IMX8MQ_CLK_DISP_DC8000_SRC 179
|
||||
#define IMX8MQ_CLK_DISP_DC8000_CG 180
|
||||
#define IMX8MQ_CLK_DISP_DC8000_PRE_DIV 181
|
||||
#define IMX8MQ_CLK_DISP_DC8000_DIV 182
|
||||
#define IMX8MQ_CLK_DISP_DC8000 123
|
||||
/* PCIE_CTRL */
|
||||
#define IMX8MQ_CLK_PCIE1_CTRL_SRC 183
|
||||
#define IMX8MQ_CLK_PCIE1_CTRL_CG 184
|
||||
#define IMX8MQ_CLK_PCIE1_CTRL_PRE_DIV 185
|
||||
#define IMX8MQ_CLK_PCIE1_CTRL_DIV 186
|
||||
#define IMX8MQ_CLK_PCIE1_CTRL 124
|
||||
/* PCIE_PHY */
|
||||
#define IMX8MQ_CLK_PCIE1_PHY_SRC 187
|
||||
#define IMX8MQ_CLK_PCIE1_PHY_CG 188
|
||||
#define IMX8MQ_CLK_PCIE1_PHY_PRE_DIV 189
|
||||
#define IMX8MQ_CLK_PCIE1_PHY_DIV 190
|
||||
#define IMX8MQ_CLK_PCIE1_PHY 125
|
||||
/* PCIE_AUX */
|
||||
#define IMX8MQ_CLK_PCIE1_AUX_SRC 191
|
||||
#define IMX8MQ_CLK_PCIE1_AUX_CG 192
|
||||
#define IMX8MQ_CLK_PCIE1_AUX_PRE_DIV 193
|
||||
#define IMX8MQ_CLK_PCIE1_AUX_DIV 194
|
||||
#define IMX8MQ_CLK_PCIE1_AUX 126
|
||||
/* DC_PIXEL */
|
||||
#define IMX8MQ_CLK_DC_PIXEL_SRC 195
|
||||
#define IMX8MQ_CLK_DC_PIXEL_CG 196
|
||||
#define IMX8MQ_CLK_DC_PIXEL_PRE_DIV 197
|
||||
#define IMX8MQ_CLK_DC_PIXEL_DIV 198
|
||||
#define IMX8MQ_CLK_DC_PIXEL 127
|
||||
/* LCDIF_PIXEL */
|
||||
#define IMX8MQ_CLK_LCDIF_PIXEL_SRC 199
|
||||
#define IMX8MQ_CLK_LCDIF_PIXEL_CG 200
|
||||
#define IMX8MQ_CLK_LCDIF_PIXEL_PRE_DIV 201
|
||||
#define IMX8MQ_CLK_LCDIF_PIXEL_DIV 202
|
||||
#define IMX8MQ_CLK_LCDIF_PIXEL 128
|
||||
/* SAI1~6 */
|
||||
#define IMX8MQ_CLK_SAI1_SRC 203
|
||||
#define IMX8MQ_CLK_SAI1_CG 204
|
||||
#define IMX8MQ_CLK_SAI1_PRE_DIV 205
|
||||
#define IMX8MQ_CLK_SAI1_DIV 206
|
||||
#define IMX8MQ_CLK_SAI1 129
|
||||
|
||||
#define IMX8MQ_CLK_SAI2_SRC 207
|
||||
#define IMX8MQ_CLK_SAI2_CG 208
|
||||
#define IMX8MQ_CLK_SAI2_PRE_DIV 209
|
||||
#define IMX8MQ_CLK_SAI2_DIV 210
|
||||
#define IMX8MQ_CLK_SAI2 130
|
||||
|
||||
#define IMX8MQ_CLK_SAI3_SRC 211
|
||||
#define IMX8MQ_CLK_SAI3_CG 212
|
||||
#define IMX8MQ_CLK_SAI3_PRE_DIV 213
|
||||
#define IMX8MQ_CLK_SAI3_DIV 214
|
||||
#define IMX8MQ_CLK_SAI3 131
|
||||
|
||||
#define IMX8MQ_CLK_SAI4_SRC 215
|
||||
#define IMX8MQ_CLK_SAI4_CG 216
|
||||
#define IMX8MQ_CLK_SAI4_PRE_DIV 217
|
||||
#define IMX8MQ_CLK_SAI4_DIV 218
|
||||
#define IMX8MQ_CLK_SAI4 132
|
||||
|
||||
#define IMX8MQ_CLK_SAI5_SRC 219
|
||||
#define IMX8MQ_CLK_SAI5_CG 220
|
||||
#define IMX8MQ_CLK_SAI5_PRE_DIV 221
|
||||
#define IMX8MQ_CLK_SAI5_DIV 222
|
||||
#define IMX8MQ_CLK_SAI5 133
|
||||
|
||||
#define IMX8MQ_CLK_SAI6_SRC 223
|
||||
#define IMX8MQ_CLK_SAI6_CG 224
|
||||
#define IMX8MQ_CLK_SAI6_PRE_DIV 225
|
||||
#define IMX8MQ_CLK_SAI6_DIV 226
|
||||
#define IMX8MQ_CLK_SAI6 134
|
||||
/* SPDIF1 */
|
||||
#define IMX8MQ_CLK_SPDIF1_SRC 227
|
||||
#define IMX8MQ_CLK_SPDIF1_CG 228
|
||||
#define IMX8MQ_CLK_SPDIF1_PRE_DIV 229
|
||||
#define IMX8MQ_CLK_SPDIF1_DIV 230
|
||||
#define IMX8MQ_CLK_SPDIF1 135
|
||||
/* SPDIF2 */
|
||||
#define IMX8MQ_CLK_SPDIF2_SRC 231
|
||||
#define IMX8MQ_CLK_SPDIF2_CG 232
|
||||
#define IMX8MQ_CLK_SPDIF2_PRE_DIV 233
|
||||
#define IMX8MQ_CLK_SPDIF2_DIV 234
|
||||
#define IMX8MQ_CLK_SPDIF2 136
|
||||
/* ENET_REF */
|
||||
#define IMX8MQ_CLK_ENET_REF_SRC 235
|
||||
#define IMX8MQ_CLK_ENET_REF_CG 236
|
||||
#define IMX8MQ_CLK_ENET_REF_PRE_DIV 237
|
||||
#define IMX8MQ_CLK_ENET_REF_DIV 238
|
||||
#define IMX8MQ_CLK_ENET_REF 137
|
||||
/* ENET_TIMER */
|
||||
#define IMX8MQ_CLK_ENET_TIMER_SRC 239
|
||||
#define IMX8MQ_CLK_ENET_TIMER_CG 240
|
||||
#define IMX8MQ_CLK_ENET_TIMER_PRE_DIV 241
|
||||
#define IMX8MQ_CLK_ENET_TIMER_DIV 242
|
||||
#define IMX8MQ_CLK_ENET_TIMER 138
|
||||
/* ENET_PHY */
|
||||
#define IMX8MQ_CLK_ENET_PHY_REF_SRC 243
|
||||
#define IMX8MQ_CLK_ENET_PHY_REF_CG 244
|
||||
#define IMX8MQ_CLK_ENET_PHY_REF_PRE_DIV 245
|
||||
#define IMX8MQ_CLK_ENET_PHY_REF_DIV 246
|
||||
#define IMX8MQ_CLK_ENET_PHY_REF 139
|
||||
/* NAND */
|
||||
#define IMX8MQ_CLK_NAND_SRC 247
|
||||
#define IMX8MQ_CLK_NAND_CG 248
|
||||
#define IMX8MQ_CLK_NAND_PRE_DIV 249
|
||||
#define IMX8MQ_CLK_NAND_DIV 250
|
||||
#define IMX8MQ_CLK_NAND 140
|
||||
/* QSPI */
|
||||
#define IMX8MQ_CLK_QSPI_SRC 251
|
||||
#define IMX8MQ_CLK_QSPI_CG 252
|
||||
#define IMX8MQ_CLK_QSPI_PRE_DIV 253
|
||||
#define IMX8MQ_CLK_QSPI_DIV 254
|
||||
#define IMX8MQ_CLK_QSPI 141
|
||||
/* USDHC1 */
|
||||
#define IMX8MQ_CLK_USDHC1_SRC 255
|
||||
#define IMX8MQ_CLK_USDHC1_CG 256
|
||||
#define IMX8MQ_CLK_USDHC1_PRE_DIV 257
|
||||
#define IMX8MQ_CLK_USDHC1_DIV 258
|
||||
#define IMX8MQ_CLK_USDHC1 142
|
||||
/* USDHC2 */
|
||||
#define IMX8MQ_CLK_USDHC2_SRC 259
|
||||
#define IMX8MQ_CLK_USDHC2_CG 260
|
||||
#define IMX8MQ_CLK_USDHC2_PRE_DIV 261
|
||||
#define IMX8MQ_CLK_USDHC2_DIV 262
|
||||
#define IMX8MQ_CLK_USDHC2 143
|
||||
/* I2C1 */
|
||||
#define IMX8MQ_CLK_I2C1_SRC 263
|
||||
#define IMX8MQ_CLK_I2C1_CG 264
|
||||
#define IMX8MQ_CLK_I2C1_PRE_DIV 265
|
||||
#define IMX8MQ_CLK_I2C1_DIV 266
|
||||
#define IMX8MQ_CLK_I2C1 144
|
||||
/* I2C2 */
|
||||
#define IMX8MQ_CLK_I2C2_SRC 267
|
||||
#define IMX8MQ_CLK_I2C2_CG 268
|
||||
#define IMX8MQ_CLK_I2C2_PRE_DIV 269
|
||||
#define IMX8MQ_CLK_I2C2_DIV 270
|
||||
#define IMX8MQ_CLK_I2C2 145
|
||||
/* I2C3 */
|
||||
#define IMX8MQ_CLK_I2C3_SRC 271
|
||||
#define IMX8MQ_CLK_I2C3_CG 272
|
||||
#define IMX8MQ_CLK_I2C3_PRE_DIV 273
|
||||
#define IMX8MQ_CLK_I2C3_DIV 274
|
||||
#define IMX8MQ_CLK_I2C3 146
|
||||
/* I2C4 */
|
||||
#define IMX8MQ_CLK_I2C4_SRC 275
|
||||
#define IMX8MQ_CLK_I2C4_CG 276
|
||||
#define IMX8MQ_CLK_I2C4_PRE_DIV 277
|
||||
#define IMX8MQ_CLK_I2C4_DIV 278
|
||||
#define IMX8MQ_CLK_I2C4 147
|
||||
/* UART1 */
|
||||
#define IMX8MQ_CLK_UART1_SRC 279
|
||||
#define IMX8MQ_CLK_UART1_CG 280
|
||||
#define IMX8MQ_CLK_UART1_PRE_DIV 281
|
||||
#define IMX8MQ_CLK_UART1_DIV 282
|
||||
#define IMX8MQ_CLK_UART1 148
|
||||
/* UART2 */
|
||||
#define IMX8MQ_CLK_UART2_SRC 283
|
||||
#define IMX8MQ_CLK_UART2_CG 284
|
||||
#define IMX8MQ_CLK_UART2_PRE_DIV 285
|
||||
#define IMX8MQ_CLK_UART2_DIV 286
|
||||
#define IMX8MQ_CLK_UART2 149
|
||||
/* UART3 */
|
||||
#define IMX8MQ_CLK_UART3_SRC 287
|
||||
#define IMX8MQ_CLK_UART3_CG 288
|
||||
#define IMX8MQ_CLK_UART3_PRE_DIV 289
|
||||
#define IMX8MQ_CLK_UART3_DIV 290
|
||||
#define IMX8MQ_CLK_UART3 150
|
||||
/* UART4 */
|
||||
#define IMX8MQ_CLK_UART4_SRC 291
|
||||
#define IMX8MQ_CLK_UART4_CG 292
|
||||
#define IMX8MQ_CLK_UART4_PRE_DIV 293
|
||||
#define IMX8MQ_CLK_UART4_DIV 294
|
||||
#define IMX8MQ_CLK_UART4 151
|
||||
/* USB_CORE_REF */
|
||||
#define IMX8MQ_CLK_USB_CORE_REF_SRC 295
|
||||
#define IMX8MQ_CLK_USB_CORE_REF_CG 296
|
||||
#define IMX8MQ_CLK_USB_CORE_REF_PRE_DIV 297
|
||||
#define IMX8MQ_CLK_USB_CORE_REF_DIV 298
|
||||
#define IMX8MQ_CLK_USB_CORE_REF 152
|
||||
/* USB_PHY_REF */
|
||||
#define IMX8MQ_CLK_USB_PHY_REF_SRC 299
|
||||
#define IMX8MQ_CLK_USB_PHY_REF_CG 300
|
||||
#define IMX8MQ_CLK_USB_PHY_REF_PRE_DIV 301
|
||||
#define IMX8MQ_CLK_USB_PHY_REF_DIV 302
|
||||
#define IMX8MQ_CLK_USB_PHY_REF 153
|
||||
/* ECSPI1 */
|
||||
#define IMX8MQ_CLK_ECSPI1_SRC 303
|
||||
#define IMX8MQ_CLK_ECSPI1_CG 304
|
||||
#define IMX8MQ_CLK_ECSPI1_PRE_DIV 305
|
||||
#define IMX8MQ_CLK_ECSPI1_DIV 306
|
||||
#define IMX8MQ_CLK_ECSPI1 154
|
||||
/* ECSPI2 */
|
||||
#define IMX8MQ_CLK_ECSPI2_SRC 307
|
||||
#define IMX8MQ_CLK_ECSPI2_CG 308
|
||||
#define IMX8MQ_CLK_ECSPI2_PRE_DIV 309
|
||||
#define IMX8MQ_CLK_ECSPI2_DIV 310
|
||||
#define IMX8MQ_CLK_ECSPI2 155
|
||||
/* PWM1 */
|
||||
#define IMX8MQ_CLK_PWM1_SRC 311
|
||||
#define IMX8MQ_CLK_PWM1_CG 312
|
||||
#define IMX8MQ_CLK_PWM1_PRE_DIV 313
|
||||
#define IMX8MQ_CLK_PWM1_DIV 314
|
||||
#define IMX8MQ_CLK_PWM1 156
|
||||
/* PWM2 */
|
||||
#define IMX8MQ_CLK_PWM2_SRC 315
|
||||
#define IMX8MQ_CLK_PWM2_CG 316
|
||||
#define IMX8MQ_CLK_PWM2_PRE_DIV 317
|
||||
#define IMX8MQ_CLK_PWM2_DIV 318
|
||||
#define IMX8MQ_CLK_PWM2 157
|
||||
/* PWM3 */
|
||||
#define IMX8MQ_CLK_PWM3_SRC 319
|
||||
#define IMX8MQ_CLK_PWM3_CG 320
|
||||
#define IMX8MQ_CLK_PWM3_PRE_DIV 321
|
||||
#define IMX8MQ_CLK_PWM3_DIV 322
|
||||
#define IMX8MQ_CLK_PWM3 158
|
||||
/* PWM4 */
|
||||
#define IMX8MQ_CLK_PWM4_SRC 323
|
||||
#define IMX8MQ_CLK_PWM4_CG 324
|
||||
#define IMX8MQ_CLK_PWM4_PRE_DIV 325
|
||||
#define IMX8MQ_CLK_PWM4_DIV 326
|
||||
#define IMX8MQ_CLK_PWM4 159
|
||||
/* GPT1 */
|
||||
#define IMX8MQ_CLK_GPT1_SRC 327
|
||||
#define IMX8MQ_CLK_GPT1_CG 328
|
||||
#define IMX8MQ_CLK_GPT1_PRE_DIV 329
|
||||
#define IMX8MQ_CLK_GPT1_DIV 330
|
||||
#define IMX8MQ_CLK_GPT1 160
|
||||
/* WDOG */
|
||||
#define IMX8MQ_CLK_WDOG_SRC 331
|
||||
#define IMX8MQ_CLK_WDOG_CG 332
|
||||
#define IMX8MQ_CLK_WDOG_PRE_DIV 333
|
||||
#define IMX8MQ_CLK_WDOG_DIV 334
|
||||
#define IMX8MQ_CLK_WDOG 161
|
||||
/* WRCLK */
|
||||
#define IMX8MQ_CLK_WRCLK_SRC 335
|
||||
#define IMX8MQ_CLK_WRCLK_CG 336
|
||||
#define IMX8MQ_CLK_WRCLK_PRE_DIV 337
|
||||
#define IMX8MQ_CLK_WRCLK_DIV 338
|
||||
#define IMX8MQ_CLK_WRCLK 162
|
||||
/* DSI_CORE */
|
||||
#define IMX8MQ_CLK_DSI_CORE_SRC 339
|
||||
#define IMX8MQ_CLK_DSI_CORE_CG 340
|
||||
#define IMX8MQ_CLK_DSI_CORE_PRE_DIV 341
|
||||
#define IMX8MQ_CLK_DSI_CORE_DIV 342
|
||||
#define IMX8MQ_CLK_DSI_CORE 163
|
||||
/* DSI_PHY */
|
||||
#define IMX8MQ_CLK_DSI_PHY_REF_SRC 343
|
||||
#define IMX8MQ_CLK_DSI_PHY_REF_CG 344
|
||||
#define IMX8MQ_CLK_DSI_PHY_REF_PRE_DIV 345
|
||||
#define IMX8MQ_CLK_DSI_PHY_REF_DIV 346
|
||||
#define IMX8MQ_CLK_DSI_PHY_REF 164
|
||||
/* DSI_DBI */
|
||||
#define IMX8MQ_CLK_DSI_DBI_SRC 347
|
||||
#define IMX8MQ_CLK_DSI_DBI_CG 348
|
||||
#define IMX8MQ_CLK_DSI_DBI_PRE_DIV 349
|
||||
#define IMX8MQ_CLK_DSI_DBI_DIV 350
|
||||
#define IMX8MQ_CLK_DSI_DBI 165
|
||||
/*DSI_ESC */
|
||||
#define IMX8MQ_CLK_DSI_ESC_SRC 351
|
||||
#define IMX8MQ_CLK_DSI_ESC_CG 352
|
||||
#define IMX8MQ_CLK_DSI_ESC_PRE_DIV 353
|
||||
#define IMX8MQ_CLK_DSI_ESC_DIV 354
|
||||
#define IMX8MQ_CLK_DSI_ESC 166
|
||||
/* CSI1_CORE */
|
||||
#define IMX8MQ_CLK_CSI1_CORE_SRC 355
|
||||
#define IMX8MQ_CLK_CSI1_CORE_CG 356
|
||||
#define IMX8MQ_CLK_CSI1_CORE_PRE_DIV 357
|
||||
#define IMX8MQ_CLK_CSI1_CORE_DIV 358
|
||||
#define IMX8MQ_CLK_CSI1_CORE 167
|
||||
/* CSI1_PHY */
|
||||
#define IMX8MQ_CLK_CSI1_PHY_REF_SRC 359
|
||||
#define IMX8MQ_CLK_CSI1_PHY_REF_CG 360
|
||||
#define IMX8MQ_CLK_CSI1_PHY_REF_PRE_DIV 361
|
||||
#define IMX8MQ_CLK_CSI1_PHY_REF_DIV 362
|
||||
#define IMX8MQ_CLK_CSI1_PHY_REF 168
|
||||
/* CSI_ESC */
|
||||
#define IMX8MQ_CLK_CSI1_ESC_SRC 363
|
||||
#define IMX8MQ_CLK_CSI1_ESC_CG 364
|
||||
#define IMX8MQ_CLK_CSI1_ESC_PRE_DIV 365
|
||||
#define IMX8MQ_CLK_CSI1_ESC_DIV 366
|
||||
#define IMX8MQ_CLK_CSI1_ESC 169
|
||||
/* CSI2_CORE */
|
||||
#define IMX8MQ_CLK_CSI2_CORE_SRC 367
|
||||
#define IMX8MQ_CLK_CSI2_CORE_CG 368
|
||||
#define IMX8MQ_CLK_CSI2_CORE_PRE_DIV 369
|
||||
#define IMX8MQ_CLK_CSI2_CORE_DIV 370
|
||||
#define IMX8MQ_CLK_CSI2_CORE 170
|
||||
/* CSI2_PHY */
|
||||
#define IMX8MQ_CLK_CSI2_PHY_REF_SRC 371
|
||||
#define IMX8MQ_CLK_CSI2_PHY_REF_CG 372
|
||||
#define IMX8MQ_CLK_CSI2_PHY_REF_PRE_DIV 373
|
||||
#define IMX8MQ_CLK_CSI2_PHY_REF_DIV 374
|
||||
#define IMX8MQ_CLK_CSI2_PHY_REF 171
|
||||
/* CSI2_ESC */
|
||||
#define IMX8MQ_CLK_CSI2_ESC_SRC 375
|
||||
#define IMX8MQ_CLK_CSI2_ESC_CG 376
|
||||
#define IMX8MQ_CLK_CSI2_ESC_PRE_DIV 377
|
||||
#define IMX8MQ_CLK_CSI2_ESC_DIV 378
|
||||
#define IMX8MQ_CLK_CSI2_ESC 172
|
||||
/* PCIE2_CTRL */
|
||||
#define IMX8MQ_CLK_PCIE2_CTRL_SRC 379
|
||||
#define IMX8MQ_CLK_PCIE2_CTRL_CG 380
|
||||
#define IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV 381
|
||||
#define IMX8MQ_CLK_PCIE2_CTRL_DIV 382
|
||||
#define IMX8MQ_CLK_PCIE2_CTRL 173
|
||||
/* PCIE2_PHY */
|
||||
#define IMX8MQ_CLK_PCIE2_PHY_SRC 383
|
||||
#define IMX8MQ_CLK_PCIE2_PHY_CG 384
|
||||
#define IMX8MQ_CLK_PCIE2_PHY_PRE_DIV 385
|
||||
#define IMX8MQ_CLK_PCIE2_PHY_DIV 386
|
||||
#define IMX8MQ_CLK_PCIE2_PHY 174
|
||||
/* PCIE2_AUX */
|
||||
#define IMX8MQ_CLK_PCIE2_AUX_SRC 387
|
||||
#define IMX8MQ_CLK_PCIE2_AUX_CG 388
|
||||
#define IMX8MQ_CLK_PCIE2_AUX_PRE_DIV 389
|
||||
#define IMX8MQ_CLK_PCIE2_AUX_DIV 390
|
||||
#define IMX8MQ_CLK_PCIE2_AUX 175
|
||||
/* ECSPI3 */
|
||||
#define IMX8MQ_CLK_ECSPI3_SRC 391
|
||||
#define IMX8MQ_CLK_ECSPI3_CG 392
|
||||
#define IMX8MQ_CLK_ECSPI3_PRE_DIV 393
|
||||
#define IMX8MQ_CLK_ECSPI3_DIV 394
|
||||
#define IMX8MQ_CLK_ECSPI3 176
|
||||
|
||||
/* CCGR clocks */
|
||||
#define IMX8MQ_CLK_A53_ROOT 395
|
||||
#define IMX8MQ_CLK_DRAM_ROOT 396
|
||||
#define IMX8MQ_CLK_ECSPI1_ROOT 397
|
||||
#define IMX8MQ_CLK_ECSPI2_ROOT 398
|
||||
#define IMX8MQ_CLK_ECSPI3_ROOT 399
|
||||
#define IMX8MQ_CLK_ENET1_ROOT 400
|
||||
#define IMX8MQ_CLK_GPT1_ROOT 401
|
||||
#define IMX8MQ_CLK_I2C1_ROOT 402
|
||||
#define IMX8MQ_CLK_I2C2_ROOT 403
|
||||
#define IMX8MQ_CLK_I2C3_ROOT 404
|
||||
#define IMX8MQ_CLK_I2C4_ROOT 405
|
||||
#define IMX8MQ_CLK_M4_ROOT 406
|
||||
#define IMX8MQ_CLK_PCIE1_ROOT 407
|
||||
#define IMX8MQ_CLK_PCIE2_ROOT 408
|
||||
#define IMX8MQ_CLK_PWM1_ROOT 409
|
||||
#define IMX8MQ_CLK_PWM2_ROOT 410
|
||||
#define IMX8MQ_CLK_PWM3_ROOT 411
|
||||
#define IMX8MQ_CLK_PWM4_ROOT 412
|
||||
#define IMX8MQ_CLK_QSPI_ROOT 413
|
||||
#define IMX8MQ_CLK_SAI1_ROOT 414
|
||||
#define IMX8MQ_CLK_SAI2_ROOT 415
|
||||
#define IMX8MQ_CLK_SAI3_ROOT 416
|
||||
#define IMX8MQ_CLK_SAI4_ROOT 417
|
||||
#define IMX8MQ_CLK_SAI5_ROOT 418
|
||||
#define IMX8MQ_CLK_SAI6_ROOT 419
|
||||
#define IMX8MQ_CLK_UART1_ROOT 420
|
||||
#define IMX8MQ_CLK_UART2_ROOT 421
|
||||
#define IMX8MQ_CLK_UART3_ROOT 422
|
||||
#define IMX8MQ_CLK_UART4_ROOT 423
|
||||
#define IMX8MQ_CLK_USB1_CTRL_ROOT 424
|
||||
#define IMX8MQ_CLK_USB2_CTRL_ROOT 425
|
||||
#define IMX8MQ_CLK_USB1_PHY_ROOT 426
|
||||
#define IMX8MQ_CLK_USB2_PHY_ROOT 427
|
||||
#define IMX8MQ_CLK_USDHC1_ROOT 428
|
||||
#define IMX8MQ_CLK_USDHC2_ROOT 429
|
||||
#define IMX8MQ_CLK_WDOG1_ROOT 430
|
||||
#define IMX8MQ_CLK_WDOG2_ROOT 431
|
||||
#define IMX8MQ_CLK_WDOG3_ROOT 432
|
||||
#define IMX8MQ_CLK_GPU_ROOT 433
|
||||
#define IMX8MQ_CLK_HEVC_ROOT 434
|
||||
#define IMX8MQ_CLK_AVC_ROOT 435
|
||||
#define IMX8MQ_CLK_VP9_ROOT 436
|
||||
#define IMX8MQ_CLK_HEVC_INTER_ROOT 437
|
||||
#define IMX8MQ_CLK_DISP_ROOT 438
|
||||
#define IMX8MQ_CLK_HDMI_ROOT 439
|
||||
#define IMX8MQ_CLK_HDMI_PHY_ROOT 440
|
||||
#define IMX8MQ_CLK_VPU_DEC_ROOT 441
|
||||
#define IMX8MQ_CLK_CSI1_ROOT 442
|
||||
#define IMX8MQ_CLK_CSI2_ROOT 443
|
||||
#define IMX8MQ_CLK_RAWNAND_ROOT 444
|
||||
#define IMX8MQ_CLK_SDMA1_ROOT 445
|
||||
#define IMX8MQ_CLK_SDMA2_ROOT 446
|
||||
#define IMX8MQ_CLK_VPU_G1_ROOT 447
|
||||
#define IMX8MQ_CLK_VPU_G2_ROOT 448
|
||||
#define IMX8MQ_CLK_A53_ROOT 177
|
||||
#define IMX8MQ_CLK_DRAM_ROOT 178
|
||||
#define IMX8MQ_CLK_ECSPI1_ROOT 179
|
||||
#define IMX8MQ_CLK_ECSPI2_ROOT 180
|
||||
#define IMX8MQ_CLK_ECSPI3_ROOT 181
|
||||
#define IMX8MQ_CLK_ENET1_ROOT 182
|
||||
#define IMX8MQ_CLK_GPT1_ROOT 183
|
||||
#define IMX8MQ_CLK_I2C1_ROOT 184
|
||||
#define IMX8MQ_CLK_I2C2_ROOT 185
|
||||
#define IMX8MQ_CLK_I2C3_ROOT 186
|
||||
#define IMX8MQ_CLK_I2C4_ROOT 187
|
||||
#define IMX8MQ_CLK_M4_ROOT 188
|
||||
#define IMX8MQ_CLK_PCIE1_ROOT 189
|
||||
#define IMX8MQ_CLK_PCIE2_ROOT 190
|
||||
#define IMX8MQ_CLK_PWM1_ROOT 191
|
||||
#define IMX8MQ_CLK_PWM2_ROOT 192
|
||||
#define IMX8MQ_CLK_PWM3_ROOT 193
|
||||
#define IMX8MQ_CLK_PWM4_ROOT 194
|
||||
#define IMX8MQ_CLK_QSPI_ROOT 195
|
||||
#define IMX8MQ_CLK_SAI1_ROOT 196
|
||||
#define IMX8MQ_CLK_SAI2_ROOT 197
|
||||
#define IMX8MQ_CLK_SAI3_ROOT 198
|
||||
#define IMX8MQ_CLK_SAI4_ROOT 199
|
||||
#define IMX8MQ_CLK_SAI5_ROOT 200
|
||||
#define IMX8MQ_CLK_SAI6_ROOT 201
|
||||
#define IMX8MQ_CLK_UART1_ROOT 202
|
||||
#define IMX8MQ_CLK_UART2_ROOT 203
|
||||
#define IMX8MQ_CLK_UART3_ROOT 204
|
||||
#define IMX8MQ_CLK_UART4_ROOT 205
|
||||
#define IMX8MQ_CLK_USB1_CTRL_ROOT 206
|
||||
#define IMX8MQ_CLK_USB2_CTRL_ROOT 207
|
||||
#define IMX8MQ_CLK_USB1_PHY_ROOT 208
|
||||
#define IMX8MQ_CLK_USB2_PHY_ROOT 209
|
||||
#define IMX8MQ_CLK_USDHC1_ROOT 210
|
||||
#define IMX8MQ_CLK_USDHC2_ROOT 211
|
||||
#define IMX8MQ_CLK_WDOG1_ROOT 212
|
||||
#define IMX8MQ_CLK_WDOG2_ROOT 213
|
||||
#define IMX8MQ_CLK_WDOG3_ROOT 214
|
||||
#define IMX8MQ_CLK_GPU_ROOT 215
|
||||
#define IMX8MQ_CLK_HEVC_ROOT 216
|
||||
#define IMX8MQ_CLK_AVC_ROOT 217
|
||||
#define IMX8MQ_CLK_VP9_ROOT 218
|
||||
#define IMX8MQ_CLK_HEVC_INTER_ROOT 219
|
||||
#define IMX8MQ_CLK_DISP_ROOT 220
|
||||
#define IMX8MQ_CLK_HDMI_ROOT 221
|
||||
#define IMX8MQ_CLK_HDMI_PHY_ROOT 222
|
||||
#define IMX8MQ_CLK_VPU_DEC_ROOT 223
|
||||
#define IMX8MQ_CLK_CSI1_ROOT 224
|
||||
#define IMX8MQ_CLK_CSI2_ROOT 225
|
||||
#define IMX8MQ_CLK_RAWNAND_ROOT 226
|
||||
#define IMX8MQ_CLK_SDMA1_ROOT 227
|
||||
#define IMX8MQ_CLK_SDMA2_ROOT 228
|
||||
#define IMX8MQ_CLK_VPU_G1_ROOT 229
|
||||
#define IMX8MQ_CLK_VPU_G2_ROOT 230
|
||||
|
||||
/* SCCG PLL GATE */
|
||||
#define IMX8MQ_SYS1_PLL_OUT 449
|
||||
#define IMX8MQ_SYS2_PLL_OUT 450
|
||||
#define IMX8MQ_SYS3_PLL_OUT 451
|
||||
#define IMX8MQ_DRAM_PLL_OUT 452
|
||||
#define IMX8MQ_SYS1_PLL_OUT 231
|
||||
#define IMX8MQ_SYS2_PLL_OUT 232
|
||||
#define IMX8MQ_SYS3_PLL_OUT 233
|
||||
#define IMX8MQ_DRAM_PLL_OUT 234
|
||||
|
||||
#define IMX8MQ_GPT_3M_CLK 453
|
||||
#define IMX8MQ_GPT_3M_CLK 235
|
||||
|
||||
#define IMX8MQ_CLK_IPG_ROOT 454
|
||||
#define IMX8MQ_CLK_IPG_AUDIO_ROOT 455
|
||||
#define IMX8MQ_CLK_SAI1_IPG 456
|
||||
#define IMX8MQ_CLK_SAI2_IPG 457
|
||||
#define IMX8MQ_CLK_SAI3_IPG 458
|
||||
#define IMX8MQ_CLK_SAI4_IPG 459
|
||||
#define IMX8MQ_CLK_SAI5_IPG 460
|
||||
#define IMX8MQ_CLK_SAI6_IPG 461
|
||||
#define IMX8MQ_CLK_IPG_ROOT 236
|
||||
#define IMX8MQ_CLK_IPG_AUDIO_ROOT 237
|
||||
#define IMX8MQ_CLK_SAI1_IPG 238
|
||||
#define IMX8MQ_CLK_SAI2_IPG 239
|
||||
#define IMX8MQ_CLK_SAI3_IPG 240
|
||||
#define IMX8MQ_CLK_SAI4_IPG 241
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#define IMX8MQ_CLK_SAI5_IPG 242
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#define IMX8MQ_CLK_SAI6_IPG 243
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/* DSI AHB/IPG clocks */
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/* rxesc clock */
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#define IMX8MQ_CLK_DSI_AHB_SRC 462
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#define IMX8MQ_CLK_DSI_AHB_CG 463
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#define IMX8MQ_CLK_DSI_AHB_PRE_DIV 464
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#define IMX8MQ_CLK_DSI_AHB_DIV 465
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#define IMX8MQ_CLK_DSI_AHB 244
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/* txesc clock */
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#define IMX8MQ_CLK_DSI_IPG_DIV 466
|
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#define IMX8MQ_CLK_DSI_IPG_DIV 245
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/* VIDEO2 PLL */
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#define IMX8MQ_VIDEO2_PLL1_REF_SEL 467
|
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#define IMX8MQ_VIDEO2_PLL1_REF_DIV 468
|
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#define IMX8MQ_VIDEO2_PLL1 469
|
||||
#define IMX8MQ_VIDEO2_PLL1_OUT 470
|
||||
#define IMX8MQ_VIDEO2_PLL1_OUT_DIV 471
|
||||
#define IMX8MQ_VIDEO2_PLL2 472
|
||||
#define IMX8MQ_VIDEO2_PLL2_DIV 473
|
||||
#define IMX8MQ_VIDEO2_PLL2_OUT 474
|
||||
#define IMX8MQ_CLK_TMU_ROOT 475
|
||||
#define IMX8MQ_CLK_TMU_ROOT 246
|
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|
||||
#define IMX8MQ_CLK_END 476
|
||||
/* Display root clocks */
|
||||
#define IMX8MQ_CLK_DISP_AXI_ROOT 247
|
||||
#define IMX8MQ_CLK_DISP_APB_ROOT 248
|
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#define IMX8MQ_CLK_DISP_RTRM_ROOT 249
|
||||
|
||||
#define IMX8MQ_CLK_OCOTP_ROOT 250
|
||||
|
||||
#define IMX8MQ_CLK_DRAM_ALT_ROOT 251
|
||||
#define IMX8MQ_CLK_DRAM_CORE 252
|
||||
|
||||
#define IMX8MQ_CLK_MU_ROOT 253
|
||||
#define IMX8MQ_VIDEO2_PLL_OUT 254
|
||||
|
||||
#define IMX8MQ_CLK_CLKO2 255
|
||||
|
||||
#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 256
|
||||
|
||||
#define IMX8MQ_CLK_CLKO1 257
|
||||
#define IMX8MQ_CLK_ARM 258
|
||||
|
||||
#define IMX8MQ_CLK_GPIO1_ROOT 259
|
||||
#define IMX8MQ_CLK_GPIO2_ROOT 260
|
||||
#define IMX8MQ_CLK_GPIO3_ROOT 261
|
||||
#define IMX8MQ_CLK_GPIO4_ROOT 262
|
||||
#define IMX8MQ_CLK_GPIO5_ROOT 263
|
||||
|
||||
#define IMX8MQ_CLK_SNVS_ROOT 264
|
||||
#define IMX8MQ_CLK_GIC 265
|
||||
|
||||
#define IMX8MQ_CLK_END 266
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
|
||||
|
|
|
|||
Loading…
Reference in a new issue