net: add MV88E6xxx DSA driver
Add a DSA driver for the MV88E6xxx compatible Ethernet switches. Cc: Marek Behún <marek.behun@nic.cz> Cc: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
This commit is contained in:
Tim Harvey
Tom Rini
parent
3b8f99a3e7
commit
01e7dd050f
3 changed files with 763 additions and 0 deletions
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@ -473,6 +473,13 @@ config LITEETH
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help
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Driver for the LiteEth Ethernet MAC from LiteX.
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config MV88E6XXX
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bool "Marvell MV88E6xxx Ethernet switch DSA driver"
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depends on DM_DSA && DM_MDIO
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help
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This driver implements a DSA switch driver for the MV88E6xxx family
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of Ethernet switches using the MDIO interface
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config MVGBE
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bool "Marvell Orion5x/Kirkwood network interface support"
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depends on ARCH_KIRKWOOD || ARCH_ORION5X
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@ -60,6 +60,7 @@ obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o
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obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o
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obj-$(CONFIG_MT7620_ETH) += mt7620-eth.o
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obj-$(CONFIG_MT7628_ETH) += mt7628-eth.o
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obj-$(CONFIG_MV88E6XXX) += mv88e6xxx.o
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obj-$(CONFIG_MVGBE) += mvgbe.o
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obj-$(CONFIG_MVMDIO) += mvmdio.o
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obj-$(CONFIG_MVNETA) += mvneta.o
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755
drivers/net/mv88e6xxx.c
Normal file
755
drivers/net/mv88e6xxx.c
Normal file
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@ -0,0 +1,755 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2022
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* Gateworks Corporation <www.gateworks.com>
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* Tim Harvey <tharvey@gateworks.com>
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*
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* (C) Copyright 2015
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* Elecsys Corporation <www.elecsyscorp.com>
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* Kevin Smith <kevin.smith@elecsyscorp.com>
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*
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* Original driver:
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Prafulla Wadaskar <prafulla@marvell.com>
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*/
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/*
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* DSA driver for mv88e6xxx ethernet switches.
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*
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* This driver configures the mv88e6xxx for basic use as a DSA switch.
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*
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* This driver was adapted from drivers/net/phy/mv88e61xx and tested
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* on the mv88e6176 via an SGMII interface.
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*/
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#include <common.h>
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#include <dm/device.h>
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#include <dm/device_compat.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <dm/of_extra.h>
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#include <linux/delay.h>
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#include <miiphy.h>
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#include <net/dsa.h>
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/* Device addresses */
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#define DEVADDR_PHY(p) (p)
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#define DEVADDR_SERDES 0x0F
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/* SMI indirection registers for multichip addressing mode */
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#define SMI_CMD_REG 0x00
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#define SMI_DATA_REG 0x01
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/* Global registers */
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#define GLOBAL1_STATUS 0x00
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#define GLOBAL1_CTRL 0x04
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/* Global 2 registers */
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#define GLOBAL2_REG_PHY_CMD 0x18
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#define GLOBAL2_REG_PHY_DATA 0x19
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#define GLOBAL2_REG_SCRATCH 0x1A
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/* Port registers */
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#define PORT_REG_STATUS 0x00
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#define PORT_REG_PHYS_CTRL 0x01
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#define PORT_REG_SWITCH_ID 0x03
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#define PORT_REG_CTRL 0x04
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/* Phy registers */
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#define PHY_REG_PAGE 0x16
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/* Phy page numbers */
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#define PHY_PAGE_COPPER 0
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#define PHY_PAGE_SERDES 1
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/* Register fields */
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#define GLOBAL1_CTRL_SWRESET BIT(15)
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#define PORT_REG_STATUS_SPEED_SHIFT 8
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#define PORT_REG_STATUS_SPEED_10 0
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#define PORT_REG_STATUS_SPEED_100 1
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#define PORT_REG_STATUS_SPEED_1000 2
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#define PORT_REG_STATUS_CMODE_MASK 0xF
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#define PORT_REG_STATUS_CMODE_SGMII 0xa
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#define PORT_REG_STATUS_CMODE_1000BASE_X 0x9
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#define PORT_REG_STATUS_CMODE_100BASE_X 0x8
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#define PORT_REG_STATUS_CMODE_RGMII 0x7
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#define PORT_REG_STATUS_CMODE_RMII 0x5
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#define PORT_REG_STATUS_CMODE_RMII_PHY 0x4
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#define PORT_REG_STATUS_CMODE_GMII 0x3
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#define PORT_REG_STATUS_CMODE_MII 0x2
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#define PORT_REG_STATUS_CMODE_MIIPHY 0x1
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#define PORT_REG_PHYS_CTRL_RGMII_DELAY_RXCLK BIT(15)
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#define PORT_REG_PHYS_CTRL_RGMII_DELAY_TXCLK BIT(14)
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#define PORT_REG_PHYS_CTRL_PCS_AN_EN BIT(10)
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#define PORT_REG_PHYS_CTRL_PCS_AN_RST BIT(9)
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#define PORT_REG_PHYS_CTRL_FC_VALUE BIT(7)
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#define PORT_REG_PHYS_CTRL_FC_FORCE BIT(6)
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#define PORT_REG_PHYS_CTRL_LINK_VALUE BIT(5)
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#define PORT_REG_PHYS_CTRL_LINK_FORCE BIT(4)
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#define PORT_REG_PHYS_CTRL_DUPLEX_VALUE BIT(3)
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#define PORT_REG_PHYS_CTRL_DUPLEX_FORCE BIT(2)
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#define PORT_REG_PHYS_CTRL_SPD1000 BIT(1)
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#define PORT_REG_PHYS_CTRL_SPD100 BIT(0)
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#define PORT_REG_PHYS_CTRL_SPD_MASK (BIT(1) | BIT(0))
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#define PORT_REG_CTRL_PSTATE_SHIFT 0
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#define PORT_REG_CTRL_PSTATE_MASK 3
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/* Field values */
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#define PORT_REG_CTRL_PSTATE_DISABLED 0
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#define PORT_REG_CTRL_PSTATE_FORWARD 3
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/*
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* Macros for building commands for indirect addressing modes. These are valid
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* for both the indirect multichip addressing mode and the PHY indirection
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* required for the writes to any PHY register.
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*/
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#define SMI_BUSY BIT(15)
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#define SMI_CMD_CLAUSE_22 BIT(12)
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#define SMI_CMD_CLAUSE_22_OP_READ (2 << 10)
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#define SMI_CMD_CLAUSE_22_OP_WRITE (1 << 10)
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#define SMI_CMD_ADDR_SHIFT 5
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#define SMI_CMD_ADDR_MASK 0x1f
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#define SMI_CMD_REG_SHIFT 0
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#define SMI_CMD_REG_MASK 0x1f
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#define SMI_CMD_READ(addr, reg) \
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(SMI_BUSY | SMI_CMD_CLAUSE_22 | SMI_CMD_CLAUSE_22_OP_READ) | \
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(((addr) & SMI_CMD_ADDR_MASK) << SMI_CMD_ADDR_SHIFT) | \
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(((reg) & SMI_CMD_REG_MASK) << SMI_CMD_REG_SHIFT)
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#define SMI_CMD_WRITE(addr, reg) \
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(SMI_BUSY | SMI_CMD_CLAUSE_22 | SMI_CMD_CLAUSE_22_OP_WRITE) | \
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(((addr) & SMI_CMD_ADDR_MASK) << SMI_CMD_ADDR_SHIFT) | \
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(((reg) & SMI_CMD_REG_MASK) << SMI_CMD_REG_SHIFT)
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/* ID register values for different switch models */
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#define PORT_SWITCH_ID_6020 0x0200
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#define PORT_SWITCH_ID_6070 0x0700
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#define PORT_SWITCH_ID_6071 0x0710
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#define PORT_SWITCH_ID_6096 0x0980
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#define PORT_SWITCH_ID_6097 0x0990
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#define PORT_SWITCH_ID_6172 0x1720
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#define PORT_SWITCH_ID_6176 0x1760
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#define PORT_SWITCH_ID_6220 0x2200
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#define PORT_SWITCH_ID_6240 0x2400
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#define PORT_SWITCH_ID_6250 0x2500
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#define PORT_SWITCH_ID_6320 0x1150
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#define PORT_SWITCH_ID_6352 0x3520
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struct mv88e6xxx_priv {
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int smi_addr;
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int id;
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int port_count; /* Number of switch ports */
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int port_reg_base; /* Base of the switch port registers */
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u8 global1; /* Offset of Switch Global 1 registers */
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u8 global2; /* Offset of Switch Global 2 registers */
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};
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/* Wait for the current SMI indirect command to complete */
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static int mv88e6xxx_smi_wait(struct udevice *dev, int smi_addr)
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{
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int val;
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u32 timeout = 100;
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do {
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val = dm_mdio_read(dev->parent, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG);
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if (val >= 0 && (val & SMI_BUSY) == 0)
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return 0;
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mdelay(1);
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} while (--timeout);
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dev_err(dev, "SMI busy timeout\n");
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return -ETIMEDOUT;
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}
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/*
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* The mv88e6xxx has three types of addresses: the smi bus address, the device
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* address, and the register address. The smi bus address distinguishes it on
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* the smi bus from other PHYs or switches. The device address determines
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* which on-chip register set you are reading/writing (the various PHYs, their
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* associated ports, or global configuration registers). The register address
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* is the offset of the register you are reading/writing.
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*
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* When the mv88e6xxx is hardware configured to have address zero, it behaves in
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* single-chip addressing mode, where it responds to all SMI addresses, using
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* the smi address as its device address. This obviously only works when this
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* is the only chip on the SMI bus. This allows the driver to access device
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* registers without using indirection. When the chip is configured to a
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* non-zero address, it only responds to that SMI address and requires indirect
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* writes to access the different device addresses.
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*/
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static int mv88e6xxx_reg_read(struct udevice *dev, int addr, int reg)
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{
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struct mv88e6xxx_priv *priv = dev_get_priv(dev);
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int smi_addr = priv->smi_addr;
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int res;
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/* In single-chip mode, the device can be addressed directly */
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if (smi_addr == 0)
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return dm_mdio_read(dev->parent, addr, MDIO_DEVAD_NONE, reg);
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/* Wait for the bus to become free */
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res = mv88e6xxx_smi_wait(dev, smi_addr);
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if (res < 0)
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return res;
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/* Issue the read command */
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res = dm_mdio_write(dev->parent, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
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SMI_CMD_READ(addr, reg));
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if (res < 0)
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return res;
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/* Wait for the read command to complete */
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res = mv88e6xxx_smi_wait(dev, smi_addr);
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if (res < 0)
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return res;
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/* Read the data */
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res = dm_mdio_read(dev->parent, smi_addr, MDIO_DEVAD_NONE, SMI_DATA_REG);
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if (res < 0)
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return res;
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return res & 0xffff;
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}
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/* See the comment above mv88e6xxx_reg_read */
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static int mv88e6xxx_reg_write(struct udevice *dev, int addr, int reg, u16 val)
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{
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struct mv88e6xxx_priv *priv = dev_get_priv(dev);
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int smi_addr = priv->smi_addr;
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int res;
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/* In single-chip mode, the device can be addressed directly */
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if (smi_addr == 0)
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return dm_mdio_write(dev->parent, addr, MDIO_DEVAD_NONE, reg, val);
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/* Wait for the bus to become free */
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res = mv88e6xxx_smi_wait(dev, smi_addr);
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if (res < 0)
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return res;
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/* Set the data to write */
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res = dm_mdio_write(dev->parent, smi_addr, MDIO_DEVAD_NONE,
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SMI_DATA_REG, val);
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if (res < 0)
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return res;
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/* Issue the write command */
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res = dm_mdio_write(dev->parent, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
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SMI_CMD_WRITE(addr, reg));
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if (res < 0)
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return res;
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/* Wait for the write command to complete */
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res = mv88e6xxx_smi_wait(dev, smi_addr);
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if (res < 0)
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return res;
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return 0;
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}
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static int mv88e6xxx_phy_wait(struct udevice *dev)
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{
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struct mv88e6xxx_priv *priv = dev_get_priv(dev);
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int val;
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u32 timeout = 100;
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do {
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val = mv88e6xxx_reg_read(dev, priv->global2, GLOBAL2_REG_PHY_CMD);
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if (val >= 0 && (val & SMI_BUSY) == 0)
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return 0;
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mdelay(1);
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} while (--timeout);
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return -ETIMEDOUT;
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}
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static int mv88e6xxx_phy_read_indirect(struct udevice *dev, int phyad, int devad, int reg)
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{
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struct mv88e6xxx_priv *priv = dev_get_priv(dev);
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int res;
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/* Issue command to read */
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res = mv88e6xxx_reg_write(dev, priv->global2,
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GLOBAL2_REG_PHY_CMD,
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SMI_CMD_READ(phyad, reg));
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/* Wait for data to be read */
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res = mv88e6xxx_phy_wait(dev);
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if (res < 0)
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return res;
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/* Read retrieved data */
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return mv88e6xxx_reg_read(dev, priv->global2,
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GLOBAL2_REG_PHY_DATA);
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}
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static int mv88e6xxx_phy_write_indirect(struct udevice *dev, int phyad,
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int devad, int reg, u16 data)
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{
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struct mv88e6xxx_priv *priv = dev_get_priv(dev);
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int res;
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/* Set the data to write */
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res = mv88e6xxx_reg_write(dev, priv->global2,
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GLOBAL2_REG_PHY_DATA, data);
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if (res < 0)
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return res;
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/* Issue the write command */
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res = mv88e6xxx_reg_write(dev, priv->global2,
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GLOBAL2_REG_PHY_CMD,
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SMI_CMD_WRITE(phyad, reg));
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if (res < 0)
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return res;
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/* Wait for command to complete */
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return mv88e6xxx_phy_wait(dev);
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}
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/* Wrapper function to make calls to phy_read_indirect simpler */
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static int mv88e6xxx_phy_read(struct udevice *dev, int phy, int reg)
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{
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return mv88e6xxx_phy_read_indirect(dev, DEVADDR_PHY(phy),
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MDIO_DEVAD_NONE, reg);
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}
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/* Wrapper function to make calls to phy_write_indirect simpler */
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static int mv88e6xxx_phy_write(struct udevice *dev, int phy, int reg, u16 val)
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{
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return mv88e6xxx_phy_write_indirect(dev, DEVADDR_PHY(phy),
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MDIO_DEVAD_NONE, reg, val);
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}
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static int mv88e6xxx_port_read(struct udevice *dev, u8 port, u8 reg)
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{
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struct mv88e6xxx_priv *priv = dev_get_priv(dev);
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return mv88e6xxx_reg_read(dev, priv->port_reg_base + port, reg);
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}
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static int mv88e6xxx_port_write(struct udevice *dev, u8 port, u8 reg, u16 val)
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{
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struct mv88e6xxx_priv *priv = dev_get_priv(dev);
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return mv88e6xxx_reg_write(dev, priv->port_reg_base + port, reg, val);
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}
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static int mv88e6xxx_set_page(struct udevice *dev, u8 phy, u8 page)
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{
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return mv88e6xxx_phy_write(dev, phy, PHY_REG_PAGE, page);
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}
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static int mv88e6xxx_get_switch_id(struct udevice *dev)
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{
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int res;
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res = mv88e6xxx_port_read(dev, 0, PORT_REG_SWITCH_ID);
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if (res < 0) {
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dev_err(dev, "Failed to read switch ID: %d\n", res);
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return res;
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}
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return res & 0xfff0;
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}
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static bool mv88e6xxx_6352_family(struct udevice *dev)
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{
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struct mv88e6xxx_priv *priv = dev_get_priv(dev);
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switch (priv->id) {
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case PORT_SWITCH_ID_6172:
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case PORT_SWITCH_ID_6176:
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case PORT_SWITCH_ID_6240:
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case PORT_SWITCH_ID_6352:
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return true;
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}
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return false;
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}
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static int mv88e6xxx_get_cmode(struct udevice *dev, u8 port)
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{
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int res;
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res = mv88e6xxx_port_read(dev, port, PORT_REG_STATUS);
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if (res < 0)
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return res;
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return res & PORT_REG_STATUS_CMODE_MASK;
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}
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static int mv88e6xxx_switch_reset(struct udevice *dev)
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{
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struct mv88e6xxx_priv *priv = dev_get_priv(dev);
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int time_ms;
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int val;
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u8 port;
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/* Disable all ports */
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for (port = 0; port < priv->port_count; port++) {
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val = mv88e6xxx_port_read(dev, port, PORT_REG_CTRL);
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if (val < 0)
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return val;
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val &= ~(PORT_REG_CTRL_PSTATE_MASK << PORT_REG_CTRL_PSTATE_SHIFT);
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val |= (PORT_REG_CTRL_PSTATE_DISABLED << PORT_REG_CTRL_PSTATE_SHIFT);
|
||||
val = mv88e6xxx_port_write(dev, port, PORT_REG_CTRL, val);
|
||||
if (val < 0)
|
||||
return val;
|
||||
}
|
||||
|
||||
/* Wait 2 ms for queues to drain */
|
||||
udelay(2000);
|
||||
|
||||
/* Reset switch */
|
||||
val = mv88e6xxx_reg_read(dev, priv->global1, GLOBAL1_CTRL);
|
||||
if (val < 0)
|
||||
return val;
|
||||
val |= GLOBAL1_CTRL_SWRESET;
|
||||
val = mv88e6xxx_reg_write(dev, priv->global1, GLOBAL1_CTRL, val);
|
||||
if (val < 0)
|
||||
return val;
|
||||
|
||||
/* Wait up to 1 second for switch to reset complete */
|
||||
for (time_ms = 1000; time_ms; time_ms--) {
|
||||
val = mv88e6xxx_reg_read(dev, priv->global1, GLOBAL1_CTRL);
|
||||
if (val >= 0 && ((val & GLOBAL1_CTRL_SWRESET) == 0))
|
||||
break;
|
||||
udelay(1000);
|
||||
}
|
||||
if (!time_ms)
|
||||
return -ETIMEDOUT;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mv88e6xxx_serdes_init(struct udevice *dev)
|
||||
{
|
||||
int val;
|
||||
|
||||
val = mv88e6xxx_set_page(dev, DEVADDR_SERDES, PHY_PAGE_SERDES);
|
||||
if (val < 0)
|
||||
return val;
|
||||
|
||||
/* Power up serdes module */
|
||||
val = mv88e6xxx_phy_read(dev, DEVADDR_SERDES, MII_BMCR);
|
||||
if (val < 0)
|
||||
return val;
|
||||
val &= ~(BMCR_PDOWN);
|
||||
val = mv88e6xxx_phy_write(dev, DEVADDR_SERDES, MII_BMCR, val);
|
||||
if (val < 0)
|
||||
return val;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is used to pre-configure the required register
|
||||
* offsets, so that the indirect register access to the PHY registers
|
||||
* is possible. This is necessary to be able to read the PHY ID
|
||||
* while driver probing or in get_phy_id(). The globalN register
|
||||
* offsets must be initialized correctly for a detected switch,
|
||||
* otherwise detection of the PHY ID won't work!
|
||||
*/
|
||||
static int mv88e6xxx_priv_reg_offs_pre_init(struct udevice *dev)
|
||||
{
|
||||
struct mv88e6xxx_priv *priv = dev_get_priv(dev);
|
||||
|
||||
/*
|
||||
* Initial 'port_reg_base' value must be an offset of existing
|
||||
* port register, then reading the ID should succeed. First, try
|
||||
* to read via port registers with device address 0x10 (88E6096
|
||||
* and compatible switches).
|
||||
*/
|
||||
priv->port_reg_base = 0x10;
|
||||
priv->id = mv88e6xxx_get_switch_id(dev);
|
||||
if (priv->id != 0xfff0) {
|
||||
priv->global1 = 0x1B;
|
||||
priv->global2 = 0x1C;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Now try via port registers with device address 0x08
|
||||
* (88E6020 and compatible switches).
|
||||
*/
|
||||
priv->port_reg_base = 0x08;
|
||||
priv->id = mv88e6xxx_get_switch_id(dev);
|
||||
if (priv->id != 0xfff0) {
|
||||
priv->global1 = 0x0F;
|
||||
priv->global2 = 0x07;
|
||||
return 0;
|
||||
}
|
||||
|
||||
dev_warn(dev, "%s Unknown ID 0x%x\n", __func__, priv->id);
|
||||
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static int mv88e6xxx_mdio_read(struct udevice *dev, int addr, int devad, int reg)
|
||||
{
|
||||
return mv88e6xxx_phy_read_indirect(dev->parent, DEVADDR_PHY(addr),
|
||||
MDIO_DEVAD_NONE, reg);
|
||||
}
|
||||
|
||||
static int mv88e6xxx_mdio_write(struct udevice *dev, int addr, int devad,
|
||||
int reg, u16 val)
|
||||
{
|
||||
return mv88e6xxx_phy_write_indirect(dev->parent, DEVADDR_PHY(addr),
|
||||
MDIO_DEVAD_NONE, reg, val);
|
||||
}
|
||||
|
||||
static const struct mdio_ops mv88e6xxx_mdio_ops = {
|
||||
.read = mv88e6xxx_mdio_read,
|
||||
.write = mv88e6xxx_mdio_write,
|
||||
};
|
||||
|
||||
static int mv88e6xxx_mdio_bind(struct udevice *dev)
|
||||
{
|
||||
char name[32];
|
||||
static int num_devices;
|
||||
|
||||
sprintf(name, "mv88e6xxx-mdio-%d", num_devices++);
|
||||
device_set_name(dev, name);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_DRIVER(mv88e6xxx_mdio) = {
|
||||
.name = "mv88e6xxx_mdio",
|
||||
.id = UCLASS_MDIO,
|
||||
.ops = &mv88e6xxx_mdio_ops,
|
||||
.bind = mv88e6xxx_mdio_bind,
|
||||
.plat_auto = sizeof(struct mdio_perdev_priv),
|
||||
};
|
||||
|
||||
static int mv88e6xxx_port_probe(struct udevice *dev, int port, struct phy_device *phy)
|
||||
{
|
||||
struct mv88e6xxx_priv *priv = dev_get_priv(dev);
|
||||
int supported;
|
||||
|
||||
switch (priv->id) {
|
||||
case PORT_SWITCH_ID_6020:
|
||||
case PORT_SWITCH_ID_6070:
|
||||
case PORT_SWITCH_ID_6071:
|
||||
supported = PHY_BASIC_FEATURES | SUPPORTED_MII;
|
||||
break;
|
||||
default:
|
||||
supported = PHY_GBIT_FEATURES;
|
||||
break;
|
||||
}
|
||||
|
||||
phy->supported &= supported;
|
||||
phy->advertising &= supported;
|
||||
|
||||
return phy_config(phy);
|
||||
}
|
||||
|
||||
static int mv88e6xxx_port_enable(struct udevice *dev, int port, struct phy_device *phy)
|
||||
{
|
||||
int val, ret;
|
||||
|
||||
dev_dbg(dev, "%s P%d phy:0x%08x %s\n", __func__, port,
|
||||
phy->phy_id, phy_string_for_interface(phy->interface));
|
||||
|
||||
if (phy->phy_id == PHY_FIXED_ID) {
|
||||
/* Physical Control register: Table 62 */
|
||||
val = mv88e6xxx_port_read(dev, port, PORT_REG_PHYS_CTRL);
|
||||
|
||||
/* configure RGMII delays for fixed link */
|
||||
switch (phy->interface) {
|
||||
case PHY_INTERFACE_MODE_RGMII:
|
||||
case PHY_INTERFACE_MODE_RGMII_ID:
|
||||
case PHY_INTERFACE_MODE_RGMII_RXID:
|
||||
case PHY_INTERFACE_MODE_RGMII_TXID:
|
||||
dev_dbg(dev, "configure internal RGMII delays\n");
|
||||
|
||||
/* RGMII delays */
|
||||
val &= ~(PORT_REG_PHYS_CTRL_RGMII_DELAY_RXCLK ||
|
||||
PORT_REG_PHYS_CTRL_RGMII_DELAY_TXCLK);
|
||||
if (phy->interface == PHY_INTERFACE_MODE_RGMII_ID ||
|
||||
phy->interface == PHY_INTERFACE_MODE_RGMII_RXID)
|
||||
val |= PORT_REG_PHYS_CTRL_RGMII_DELAY_RXCLK;
|
||||
if (phy->interface == PHY_INTERFACE_MODE_RGMII_ID ||
|
||||
phy->interface == PHY_INTERFACE_MODE_RGMII_TXID)
|
||||
val |= PORT_REG_PHYS_CTRL_RGMII_DELAY_TXCLK;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Force Link */
|
||||
val |= PORT_REG_PHYS_CTRL_LINK_VALUE |
|
||||
PORT_REG_PHYS_CTRL_LINK_FORCE;
|
||||
|
||||
ret = mv88e6xxx_port_write(dev, port, PORT_REG_PHYS_CTRL, val);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
if (mv88e6xxx_6352_family(dev)) {
|
||||
/* validate interface type */
|
||||
dev_dbg(dev, "validate interface type\n");
|
||||
val = mv88e6xxx_get_cmode(dev, port);
|
||||
if (val < 0)
|
||||
return val;
|
||||
switch (phy->interface) {
|
||||
case PHY_INTERFACE_MODE_RGMII:
|
||||
case PHY_INTERFACE_MODE_RGMII_RXID:
|
||||
case PHY_INTERFACE_MODE_RGMII_TXID:
|
||||
case PHY_INTERFACE_MODE_RGMII_ID:
|
||||
if (val != PORT_REG_STATUS_CMODE_RGMII)
|
||||
goto mismatch;
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_1000BASEX:
|
||||
if (val != PORT_REG_STATUS_CMODE_1000BASE_X)
|
||||
goto mismatch;
|
||||
break;
|
||||
mismatch:
|
||||
default:
|
||||
dev_err(dev, "Mismatched PHY mode %s on port %d!\n",
|
||||
phy_string_for_interface(phy->interface), port);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* enable port */
|
||||
val = mv88e6xxx_port_read(dev, port, PORT_REG_CTRL);
|
||||
if (val < 0)
|
||||
return val;
|
||||
val &= ~(PORT_REG_CTRL_PSTATE_MASK << PORT_REG_CTRL_PSTATE_SHIFT);
|
||||
val |= (PORT_REG_CTRL_PSTATE_FORWARD << PORT_REG_CTRL_PSTATE_SHIFT);
|
||||
val = mv88e6xxx_port_write(dev, port, PORT_REG_CTRL, val);
|
||||
if (val < 0)
|
||||
return val;
|
||||
|
||||
return phy_startup(phy);
|
||||
}
|
||||
|
||||
static void mv88e6xxx_port_disable(struct udevice *dev, int port, struct phy_device *phy)
|
||||
{
|
||||
int val;
|
||||
|
||||
dev_dbg(dev, "%s P%d phy:0x%08x %s\n", __func__, port,
|
||||
phy->phy_id, phy_string_for_interface(phy->interface));
|
||||
|
||||
val = mv88e6xxx_port_read(dev, port, PORT_REG_CTRL);
|
||||
val &= ~(PORT_REG_CTRL_PSTATE_MASK << PORT_REG_CTRL_PSTATE_SHIFT);
|
||||
val |= (PORT_REG_CTRL_PSTATE_DISABLED << PORT_REG_CTRL_PSTATE_SHIFT);
|
||||
mv88e6xxx_port_write(dev, port, PORT_REG_CTRL, val);
|
||||
}
|
||||
|
||||
static const struct dsa_ops mv88e6xxx_dsa_ops = {
|
||||
.port_probe = mv88e6xxx_port_probe,
|
||||
.port_enable = mv88e6xxx_port_enable,
|
||||
.port_disable = mv88e6xxx_port_disable,
|
||||
};
|
||||
|
||||
/* bind and probe the switch mdios */
|
||||
static int mv88e6xxx_probe_mdio(struct udevice *dev)
|
||||
{
|
||||
struct udevice *mdev;
|
||||
const char *name;
|
||||
ofnode node;
|
||||
int ret;
|
||||
|
||||
/* bind phy ports of mdio child node to mv88e6xxx_mdio device */
|
||||
node = dev_read_subnode(dev, "mdio");
|
||||
if (!ofnode_valid(node))
|
||||
return 0;
|
||||
|
||||
name = ofnode_get_name(node);
|
||||
ret = device_bind_driver_to_node(dev,
|
||||
"mv88e6xxx_mdio",
|
||||
name, node, NULL);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to bind %s: %d\n", name, ret);
|
||||
} else {
|
||||
/* need to probe it as there is no compatible to do so */
|
||||
ret = uclass_get_device_by_ofnode(UCLASS_MDIO, node, &mdev);
|
||||
if (ret)
|
||||
dev_err(dev, "failed to probe %s: %d\n", name, ret);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mv88e6xxx_probe(struct udevice *dev)
|
||||
{
|
||||
struct dsa_pdata *dsa_pdata = dev_get_uclass_plat(dev);
|
||||
struct mv88e6xxx_priv *priv = dev_get_priv(dev);
|
||||
int val, ret;
|
||||
|
||||
if (ofnode_valid(dev_ofnode(dev)) &&
|
||||
!ofnode_is_enabled(dev_ofnode(dev))) {
|
||||
dev_dbg(dev, "switch disabled\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* probe internal mdio bus */
|
||||
ret = mv88e6xxx_probe_mdio(dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = mv88e6xxx_priv_reg_offs_pre_init(dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
dev_dbg(dev, "ID=0x%x PORT_BASE=0x%02x GLOBAL1=0x%02x GLOBAL2=0x%02x\n",
|
||||
priv->id, priv->port_reg_base, priv->global1, priv->global2);
|
||||
switch (priv->id) {
|
||||
case PORT_SWITCH_ID_6096:
|
||||
case PORT_SWITCH_ID_6097:
|
||||
case PORT_SWITCH_ID_6172:
|
||||
case PORT_SWITCH_ID_6176:
|
||||
case PORT_SWITCH_ID_6240:
|
||||
case PORT_SWITCH_ID_6352:
|
||||
priv->port_count = 11;
|
||||
break;
|
||||
case PORT_SWITCH_ID_6020:
|
||||
case PORT_SWITCH_ID_6070:
|
||||
case PORT_SWITCH_ID_6071:
|
||||
case PORT_SWITCH_ID_6220:
|
||||
case PORT_SWITCH_ID_6250:
|
||||
case PORT_SWITCH_ID_6320:
|
||||
priv->port_count = 7;
|
||||
break;
|
||||
default:
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
ret = mv88e6xxx_switch_reset(dev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
if (mv88e6xxx_6352_family(dev)) {
|
||||
val = mv88e6xxx_get_cmode(dev, dsa_pdata->cpu_port);
|
||||
if (val < 0)
|
||||
return val;
|
||||
/* initialize serdes */
|
||||
if (val == PORT_REG_STATUS_CMODE_100BASE_X ||
|
||||
val == PORT_REG_STATUS_CMODE_1000BASE_X ||
|
||||
val == PORT_REG_STATUS_CMODE_SGMII) {
|
||||
ret = mv88e6xxx_serdes_init(dev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id mv88e6xxx_ids[] = {
|
||||
{ .compatible = "marvell,mv88e6085" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(mv88e6xxx) = {
|
||||
.name = "mv88e6xxx",
|
||||
.id = UCLASS_DSA,
|
||||
.of_match = mv88e6xxx_ids,
|
||||
.probe = mv88e6xxx_probe,
|
||||
.ops = &mv88e6xxx_dsa_ops,
|
||||
.priv_auto = sizeof(struct mv88e6xxx_priv),
|
||||
};
|
||||
Loading…
Reference in a new issue