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pci: pcie_dw_rockchip: Support max_link_speed dts property

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Add support for max_link_speed specified in the PCI DT binding.

Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
[eugen.hristev@collabora.com: port to latest API, set default correctly,
align to 80 chars]
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
[jonas@kwiboo.se: switch to dev_read_u32_default]
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Jon Lin 2023-04-27 10:35:33 +03:00 committed by Kever Yang
parent 5374480395
commit 014a31907a
1 changed files with 5 additions and 1 deletions
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6
drivers/pci/pcie_dw_rockchip.c
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@ -42,6 +42,7 @@ struct rk_pcie {
struct clk_bulk clks;
struct reset_ctl_bulk rsts;
struct gpio_desc rst_gpio;
u32 gen;
};
/* Parameters for the waiting for iATU enabled routine */
@ -331,7 +332,7 @@ static int rockchip_pcie_init_port(struct udevice *dev)
rk_pcie_writel_apb(priv, 0x0, 0xf00040);
pcie_dw_setup_host(&priv->dw);
ret = rk_pcie_link_up(priv, LINK_SPEED_GEN_3);
ret = rk_pcie_link_up(priv, priv->gen);
if (ret < 0)
goto err_link_up;
@ -397,6 +398,9 @@ static int rockchip_pcie_parse_dt(struct udevice *dev)
goto rockchip_pcie_parse_dt_err_phy_get_by_index;
}
priv->gen = dev_read_u32_default(dev, "max-link-speed",
LINK_SPEED_GEN_3);
return 0;
rockchip_pcie_parse_dt_err_phy_get_by_index: