imx: Add support for i.MX28 based XEA board
This patch introduces support for i.MX28 based XEA board. This board supports DM/DTS in U-Boot proper as well as DM aware drivers in SPL (u-boot.sb) by using OF_PLATDATA. More detailed information regarding usage of it can be found in ./board/liebherr/xea/README file. U-Boot SPL 2019.10-rc1-00233-g6aa549f05c (Aug 12 2019 - 09:23:36 +0200) Trying to boot from MMC1 MMC0: Command 8 timeout (status 0xf0344020) mmc_load_image_raw_sector: mmc block read error U-Boot 2019.10-rc1-00233-g6aa549f05c (Aug 12 2019 - 09:23:36 +0200) CPU: Freescale i.MX28 rev1.2 at 454 MHz BOOT: SSP SPI #3, master, 3V3 NOR Model: Liebherr (LWE) XEA i.MX28 Board DRAM: 128 MiB MMC: MXS MMC: 0 Loading Environment from SPI Flash... SF: Detected n25q128a13 with page size 256 Bytes, erase size 64 KiB, total 16 MiB OK In: serial Out: serial Err: serial Net: Warning: ethernet@800f0000 (eth0) using random MAC address - ce:e1:9e:46:f3:a2 eth0: ethernet@800f0000 Hit any key to stop autoboot: 0 Signed-off-by: Lukasz Majewski <lukma@denx.de>
This commit is contained in:
Lukasz Majewski
Stefano Babic
parent
227cb30047
commit
010e58d448
12 changed files with 1028 additions and 0 deletions
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@ -570,6 +570,9 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
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vf610-pcm052.dtb \
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vf610-bk4r1.dtb
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dtb-$(CONFIG_MX28) += \
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imx28-xea.dtb
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dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \
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imx53-kp.dtb \
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imx53-m53menlo.dtb
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46
arch/arm/dts/imx28-xea-u-boot.dtsi
Normal file
46
arch/arm/dts/imx28-xea-u-boot.dtsi
Normal file
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@ -0,0 +1,46 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
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*
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* SPDX-License-Identifier: GPL-2.0+ or X11
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*/
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/*
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* The minimal augmentation DTS U-Boot file to allow eMMC driver
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* configuration in SPL for falcon boot.
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*/
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#include "imx28-u-boot.dtsi"
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/ {
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apb@80000000 {
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u-boot,dm-spl;
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apbh@80000000 {
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u-boot,dm-spl;
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};
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apbx@80040000 {
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u-boot,dm-spl;
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};
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};
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};
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&clks {
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u-boot,dm-spl;
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};
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&gpio0 {
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u-boot,dm-spl;
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};
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&pinctrl {
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u-boot,dm-spl;
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};
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&ssp0 {
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u-boot,dm-spl;
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};
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&ssp3 {
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u-boot,dm-spl;
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};
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110
arch/arm/dts/imx28-xea.dts
Normal file
110
arch/arm/dts/imx28-xea.dts
Normal file
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@ -0,0 +1,110 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
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*
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* SPDX-License-Identifier: GPL-2.0+ or X11
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*
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*/
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/dts-v1/;
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#include "imx28.dtsi"
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/ {
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model = "Liebherr (LWE) XEA i.MX28 Board";
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compatible = "lwe,xea", "fsl,imx28";
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aliases {
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spi3 = &ssp3;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x40000000 0x10000000>;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "3P3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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reg_fec_3v3: regulator-fec-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "fec-3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
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};
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};
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&mac0 {
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phy-mode = "rmii";
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pinctrl-names = "default";
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pinctrl-0 = <&mac0_pins_a>;
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phy-supply = <®_fec_3v3>;
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phy-reset-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <1>;
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phy-reset-post-delay = <1>;
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status = "okay";
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fixed-link {
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speed = <100>;
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full-duplex;
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};
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};
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&ssp0 {
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compatible = "fsl,imx28-mmc";
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_8bit_pins_a>;
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bus-width = <8>;
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vmmc-supply = <®_3p3v>;
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non-removable;
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status = "okay";
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};
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&ssp3 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx28-spi";
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pinctrl-names = "default";
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pinctrl-0 = <&spi3_pins_b>;
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status = "okay";
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spi-max-frequency = <40000000>;
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num-cs = <2>;
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flash0: s25fl256s@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <40000000>;
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reg = <0>;
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partition@0 {
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label = "SPL (spi)";
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reg = <0x0 0x10000>;
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read-only;
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};
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partition@1 {
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label = "u-boot (spi)";
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reg = <0x10000 0x70000>;
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read-only;
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};
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partition@2 {
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label = "uboot-env (spi)";
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reg = <0x80000 0x20000>;
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};
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partition@3 {
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label = "kernel (spi)";
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reg = <0x100000 0x400000>;
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};
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partition@4 {
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label = "swupdate (spi)";
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reg = <0x50000 0x800000>;
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};
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};
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};
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@ -60,6 +60,9 @@ config TARGET_SC_SPS_1
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config TARGET_TS4600
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bool "Support TS4600"
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config TARGET_XEA
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bool "Support XEA"
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endchoice
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config SYS_SOC
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@ -67,6 +70,7 @@ config SYS_SOC
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source "board/bluegiga/apx4devkit/Kconfig"
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source "board/freescale/mx28evk/Kconfig"
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source "board/liebherr/xea/Kconfig"
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source "board/ppcag/bg0900/Kconfig"
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source "board/schulercontrol/sc_sps_1/Kconfig"
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source "board/technologic/ts4600/Kconfig"
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24
board/liebherr/xea/Kconfig
Normal file
24
board/liebherr/xea/Kconfig
Normal file
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@ -0,0 +1,24 @@
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if TARGET_XEA
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config SYS_BOARD
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default "xea"
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config SYS_VENDOR
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default "liebherr"
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config SYS_SOC
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default "mxs"
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config SYS_CONFIG_NAME
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default "xea"
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config ENV_SIZE
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default 0x2000
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config ENV_SECT_SIZE
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default 0x10000 if ENV_IS_IN_SPI_FLASH
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config ENV_OFFSET
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default 0x80000 if ENV_IS_IN_SPI_FLASH
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endif
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6
board/liebherr/xea/MAINTAINERS
Normal file
6
board/liebherr/xea/MAINTAINERS
Normal file
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@ -0,0 +1,6 @@
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XEA BOARD
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M: Lukasz Majewski <lukma@denx.de>
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S: Maintained
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F: board/liebherr/xea/
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F: include/configs/xea.h
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F: configs/imx28_xea_defconfig
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12
board/liebherr/xea/Makefile
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12
board/liebherr/xea/Makefile
Normal file
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@ -0,0 +1,12 @@
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#
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# (C) Copyright 2019
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# Lukasz Majewski, DENX Software Engineering, lukma@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := xea.o
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ifdef CONFIG_SPL_BUILD
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obj-y += spl_xea.o
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endif
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63
board/liebherr/xea/README
Normal file
63
board/liebherr/xea/README
Normal file
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@ -0,0 +1,63 @@
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Building SPL/U-Boot for xea board
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=================================
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Setup environment, configure and build, e.g. by:
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$ make imx28_xea_defconfig
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$ make -j4 u-boot.sb u-boot.img
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Now you should see u-boot.sb and u-boot.img files in the build directory.
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Booting
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=======
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The boot ROM loads SPL from SPI NOR flash into SRAM. SPL configures
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DRAM and loads either a Linux kernel (falcon mode) or, if the rescue
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pin is asserted, the main U-Boot. Both kernel and U-Boot reside in
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eMMC boot partition 0. For redundancy, a copy of U-Boot is also
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stored in SPI flash. If a valid kernel image is not found, U-Boot is
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loaded from eMMC or, if this fails, SPI flash.
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Boot area layout
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----------------
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SPI NOR
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Offset Function File
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------------------------------------------
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0x00000000 SPL u-boot.sb
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0x00010000 U-Boot u-boot.img
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0x00080000 Environment
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eMMC
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Offset Function File
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------------------------------------------
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0x00000000 U-Boot u-boot.img
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0x00080000 Devicetree imx28-bttc.dtb
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0x00100000 Kernel uImage
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Falcon mode
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===========
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In falcon mode, the default, SPL loads the kernel and devicetree
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directly. For this to work, the stored devicetree must include
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correct "memory" and "chosen" nodes as these are not updated by SPL
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before booting the kernel.
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Updating from U-Boot
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====================
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The default U-Boot environment includes command sequences to update
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SPL, U-Boot, and kernel over TFTP. These are as follows:
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- update_spl: writes u-boot.sb to SPI NOR
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- update_uboot: writes u-boot.img to eMMC and SPI NOR
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- update_kernel: writes kernel and devicetree to eMMC
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They can be invoked at the U-Boot prompt using the "run" command,
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e.g. "run update_spl" to update the SPL.
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These update commands download the above-named files from the
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${hostname} directory on the server provided by DHCP.
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303
board/liebherr/xea/spl_xea.c
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303
board/liebherr/xea/spl_xea.c
Normal file
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@ -0,0 +1,303 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* DENX M28 Boot setup
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*
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* Copyright (C) 2019 DENX Software Engineering
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
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*
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* Copyright (C) 2018 DENX Software Engineering
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* Måns Rullgård, DENX Software Engineering, mans@mansr.com
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*/
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#include <common.h>
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#include <config.h>
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#include <asm/io.h>
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#include <asm/arch/iomux-mx28.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
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#define MUX_CONFIG_BOOT (MXS_PAD_3V3 | MXS_PAD_PULLUP)
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#define MUX_CONFIG_TSC (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
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#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
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#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
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#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_NOPULL)
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#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
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const iomux_cfg_t iomux_setup[] = {
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/* AUART0 IRDA */
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MX28_PAD_AUART0_RX__AUART0_RX,
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MX28_PAD_AUART0_TX__AUART0_TX,
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/* AUART 4 RS422 */
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MX28_PAD_AUART0_CTS__AUART4_RX,
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MX28_PAD_AUART0_RTS__AUART4_TX,
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/* USB0 */
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MX28_PAD_AUART1_CTS__USB0_OVERCURRENT,
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MX28_PAD_AUART1_RTS__USB0_ID,
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MX28_PAD_LCD_VSYNC__GPIO_1_28, /* PRW_On */
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/* USB1 */
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MX28_PAD_PWM2__USB1_OVERCURRENT,
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/* eMMC */
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MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DETECT__GPIO_2_9, /* Reset for eMMC */
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MX28_PAD_SSP0_SCK__SSP0_SCK | MUX_CONFIG_SSP0,
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/* DIG Keys */
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MX28_PAD_GPMI_D00__GPIO_0_0,
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MX28_PAD_GPMI_D01__GPIO_0_1,
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MX28_PAD_GPMI_D02__GPIO_0_2,
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MX28_PAD_GPMI_D03__GPIO_0_3,
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MX28_PAD_GPMI_D04__GPIO_0_4,
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MX28_PAD_GPMI_D05__GPIO_0_5,
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MX28_PAD_GPMI_D06__GPIO_0_6,
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MX28_PAD_GPMI_D07__GPIO_0_7,
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/* ADR_0-2 */
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MX28_PAD_GPMI_CE1N__GPIO_0_17,
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MX28_PAD_GPMI_CE2N__GPIO_0_18,
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MX28_PAD_GPMI_CE3N__GPIO_0_19,
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/* Read Keys */
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MX28_PAD_GPMI_RDY0__GPIO_0_20,
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/* LATCH_EN */
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MX28_PAD_GPMI_RDY1__GPIO_0_21,
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/* Power off */
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MX28_PAD_GPMI_RDN__GPIO_0_24,
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/* I2C1 Touch */
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MX28_PAD_AUART2_CTS__GPIO_3_10,
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MX28_PAD_AUART2_RTS__GPIO_3_11,
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MX28_PAD_GPMI_RDY2__GPIO_0_22, /* Touch Reset */
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/* TIVA */
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MX28_PAD_AUART1_RX__SSP2_CARD_DETECT,
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MX28_PAD_SSP2_MISO__SSP2_D0,
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MX28_PAD_SSP2_MOSI__SSP2_CMD,
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MX28_PAD_SSP2_SCK__SSP2_SCK,
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MX28_PAD_SSP2_SS0__SSP2_D3,
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MX28_PAD_SSP2_SS1__GPIO_2_20,
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MX28_PAD_SSP2_SS2__GPIO_2_21,
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/* SPI3 NOR-Flash */
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MX28_PAD_AUART1_TX__SSP3_CARD_DETECT,
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MX28_PAD_AUART2_RX__SSP3_D1,
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MX28_PAD_AUART2_TX__SSP3_D2,
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MX28_PAD_SSP3_MISO__SSP3_D0,
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MX28_PAD_SSP3_MOSI__SSP3_CMD,
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MX28_PAD_SSP3_SCK__SSP3_SCK,
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MX28_PAD_SSP3_SS0__SSP3_D3,
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/* NOR-Flash CMD */
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MX28_PAD_LCD_RS__GPIO_1_26, /* Hold */
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MX28_PAD_LCD_WR_RWN__GPIO_1_25, /* write protect */
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/* I2C0 Codec */
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MX28_PAD_I2C0_SCL__I2C0_SCL,
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MX28_PAD_I2C0_SDA__I2C0_SDA,
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/* I2S Codec */
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MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK,
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MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK,
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MX28_PAD_SAIF0_MCLK__SAIF0_MCLK,
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MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0,
|
||||
MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0,
|
||||
|
||||
/* PWR-Hold */
|
||||
MX28_PAD_SPDIF__GPIO_3_27,
|
||||
|
||||
/* EMI */
|
||||
MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
|
||||
|
||||
MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
|
||||
MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
|
||||
|
||||
/* Uart3 Bluetooth-Interface */
|
||||
MX28_PAD_AUART3_CTS__AUART3_CTS,
|
||||
MX28_PAD_AUART3_RTS__AUART3_RTS,
|
||||
MX28_PAD_AUART3_RX__AUART3_RX,
|
||||
MX28_PAD_AUART3_TX__AUART3_TX,
|
||||
|
||||
/* framebuffer */
|
||||
MX28_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD,
|
||||
MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
|
||||
MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
|
||||
MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
|
||||
MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
|
||||
MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
|
||||
MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
|
||||
MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
|
||||
MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
|
||||
MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
|
||||
MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
|
||||
MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
|
||||
MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
|
||||
MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
|
||||
MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
|
||||
MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
|
||||
MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
|
||||
MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
|
||||
MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
|
||||
MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD,
|
||||
MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD,
|
||||
MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD,
|
||||
MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
|
||||
MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
|
||||
MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
|
||||
MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD,
|
||||
MX28_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
|
||||
MX28_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD,
|
||||
MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD,
|
||||
MX28_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD,
|
||||
|
||||
/* DUART RS232 */
|
||||
MX28_PAD_PWM0__DUART_RX,
|
||||
MX28_PAD_PWM1__DUART_TX,
|
||||
|
||||
/* FEC Ethernet */
|
||||
MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
|
||||
MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET,
|
||||
MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET,
|
||||
MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
|
||||
MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
|
||||
MX28_PAD_ENET0_RX_CLK__GPIO_4_13, /* Phy Interrupt */
|
||||
MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
|
||||
MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
|
||||
MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
|
||||
MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
|
||||
MX28_PAD_ENET0_TX_CLK__GPIO_4_5, /* n.c. */
|
||||
MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
|
||||
MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
|
||||
MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
|
||||
MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
|
||||
MX28_PAD_SSP1_CMD__GPIO_2_13, /* PHY reset */
|
||||
|
||||
/* TIVA boot control */
|
||||
MX28_PAD_GPMI_RDY3__GPIO_0_23 | MUX_CONFIG_BOOT, /* TIVA0 */
|
||||
MX28_PAD_GPMI_WRN__GPIO_0_25 | MUX_CONFIG_BOOT, /* TIVA1 */
|
||||
};
|
||||
|
||||
u32 mxs_dram_vals[] = {
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000100, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00010101, 0x01010101,
|
||||
0x000f0f01, 0x0f02010a, 0x00000000, 0x00010101,
|
||||
0x00000100, 0x00000100, 0x00000000, 0x00000002,
|
||||
0x01010000, 0x07080403, 0x07005303, 0x0b0000c8,
|
||||
0x0200a0c1, 0x0002040c, 0x0038430a, 0x04290322,
|
||||
0x02040203, 0x00c8002b, 0x00000000, 0x00000000,
|
||||
0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
|
||||
0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
|
||||
0x00000003, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000612, 0x01000102,
|
||||
0x06120612, 0x00000200, 0x00020007, 0xf4004a27,
|
||||
0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07400300,
|
||||
0x07400300, 0x07400300, 0x07400300, 0x00000005,
|
||||
0x00000000, 0x00000000, 0x01000000, 0x00000000,
|
||||
0x00000001, 0x000f1133, 0x00000000, 0x00001f04,
|
||||
0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
|
||||
0x00001f04, 0x00001f04, 0x00001f04, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00010000, 0x00030404,
|
||||
0x00000002, 0x00000000, 0x00000000, 0x00000000,
|
||||
0x00000000, 0x00000000, 0x00000000, 0x01010000,
|
||||
0x01000000, 0x03030000, 0x00010303, 0x01020202,
|
||||
0x00000000, 0x02040101, 0x21002103, 0x00061200,
|
||||
0x06120612, 0x00000642, 0x00000000, 0x00000004,
|
||||
0x00000000, 0x00000080, 0x00000000, 0x00000000,
|
||||
0x00000000, 0xffffffff
|
||||
};
|
||||
|
||||
void lowlevel_init(void)
|
||||
{
|
||||
struct mxs_pinctrl_regs *pinctrl_regs =
|
||||
(struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE;
|
||||
|
||||
/* Set EMI drive strength */
|
||||
writel(0x00003fff, &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_clr);
|
||||
writel(0x00002aaa, &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);
|
||||
|
||||
mxs_common_spl_init(0, NULL, iomux_setup, ARRAY_SIZE(iomux_setup));
|
||||
}
|
||||
153
board/liebherr/xea/xea.c
Normal file
153
board/liebherr/xea/xea.c
Normal file
|
|
@ -0,0 +1,153 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* XEA iMX28 board
|
||||
*
|
||||
* Copyright (C) 2019 DENX Software Engineering
|
||||
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
|
||||
*
|
||||
* Copyright (C) 2018 DENX Software Engineering
|
||||
* Måns Rullgård, DENX Software Engineering, mans@mansr.com
|
||||
*
|
||||
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
|
||||
* on behalf of DENX Software Engineering GmbH
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/iomux-mx28.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <linux/mii.h>
|
||||
#include <miiphy.h>
|
||||
#include <netdev.h>
|
||||
#include <errno.h>
|
||||
#include <usb.h>
|
||||
#include <serial.h>
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#include <spl.h>
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
* Functions
|
||||
*/
|
||||
|
||||
static void init_clocks(void)
|
||||
{
|
||||
/* IO0 clock at 480MHz */
|
||||
mxs_set_ioclk(MXC_IOCLK0, 480000);
|
||||
/* IO1 clock at 480MHz */
|
||||
mxs_set_ioclk(MXC_IOCLK1, 480000);
|
||||
|
||||
/* SSP0 clock at 96MHz */
|
||||
mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
|
||||
/* SSP2 clock at 160MHz */
|
||||
mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
|
||||
/* SSP3 clock at 96MHz */
|
||||
mxs_set_sspclk(MXC_SSPCLK3, 96000, 0);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
void board_init_f(ulong arg)
|
||||
{
|
||||
init_clocks();
|
||||
preloader_console_init();
|
||||
}
|
||||
|
||||
static int boot_tiva0, boot_tiva1;
|
||||
|
||||
/* Check if TIVAs request booting via U-Boot proper */
|
||||
void spl_board_init(void)
|
||||
{
|
||||
struct gpio_desc btiva0, btiva1;
|
||||
int ret;
|
||||
|
||||
ret = dm_gpio_lookup_name("GPIO0_23", &btiva0);
|
||||
if (ret)
|
||||
printf("Cannot get GPIO0_23\n");
|
||||
|
||||
ret = dm_gpio_lookup_name("GPIO0_25", &btiva1);
|
||||
if (ret)
|
||||
printf("Cannot get GPIO0_25\n");
|
||||
|
||||
ret = dm_gpio_request(&btiva0, "boot-tiva0");
|
||||
if (ret)
|
||||
printf("Cannot request GPIO0_23\n");
|
||||
|
||||
ret = dm_gpio_request(&btiva1, "boot-tiva1");
|
||||
if (ret)
|
||||
printf("Cannot request GPIO0_25\n");
|
||||
|
||||
dm_gpio_set_dir_flags(&btiva0, GPIOD_IS_IN);
|
||||
dm_gpio_set_dir_flags(&btiva1, GPIOD_IS_IN);
|
||||
|
||||
udelay(1000);
|
||||
|
||||
boot_tiva0 = dm_gpio_get_value(&btiva0);
|
||||
boot_tiva1 = dm_gpio_get_value(&btiva1);
|
||||
}
|
||||
|
||||
void board_boot_order(u32 *spl_boot_list)
|
||||
{
|
||||
spl_boot_list[0] = BOOT_DEVICE_MMC1;
|
||||
spl_boot_list[1] = BOOT_DEVICE_SPI;
|
||||
}
|
||||
|
||||
int spl_start_uboot(void)
|
||||
{
|
||||
/* break into full u-boot on 'c' */
|
||||
if (serial_tstc() && serial_getc() == 'c')
|
||||
return 1;
|
||||
|
||||
debug("%s: btiva0: %d btiva1: %d\n", __func__, boot_tiva0, boot_tiva1);
|
||||
return !boot_tiva0 || !boot_tiva1;
|
||||
}
|
||||
#else
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
init_clocks();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
struct gpio_desc phy_rst;
|
||||
int ret;
|
||||
|
||||
/* Address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
|
||||
|
||||
cpu_eth_init(NULL);
|
||||
|
||||
/* PHY INT#/PWDN# */
|
||||
ret = dm_gpio_lookup_name("GPIO4_13", &phy_rst);
|
||||
if (ret) {
|
||||
printf("Cannot get GPIO4_13\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = dm_gpio_request(&phy_rst, "phy-rst");
|
||||
if (ret) {
|
||||
printf("Cannot request GPIO4_13\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
dm_gpio_set_dir_flags(&phy_rst, GPIOD_IS_IN);
|
||||
udelay(1000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
return mxs_dram_init();
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SPL_BUILD */
|
||||
108
configs/imx28_xea_defconfig
Normal file
108
configs/imx28_xea_defconfig
Normal file
|
|
@ -0,0 +1,108 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_SPL_SYS_THUMB_BUILD=y
|
||||
CONFIG_ARCH_MX28=y
|
||||
CONFIG_SYS_TEXT_BASE=0x40002000
|
||||
CONFIG_SPL_GPIO_SUPPORT=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x800
|
||||
CONFIG_SPL_DM_SPI=y
|
||||
CONFIG_TARGET_XEA=y
|
||||
CONFIG_SPL_MMC_SUPPORT=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI_SUPPORT=y
|
||||
CONFIG_SPL_TEXT_BASE=0x1000
|
||||
CONFIG_FIT=y
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0
|
||||
CONFIG_SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG=y
|
||||
CONFIG_SPL_DMA_SUPPORT=y
|
||||
CONFIG_SPL_DM_GPIO=y
|
||||
CONFIG_SPL_FORCE_MMC_BOOT=y
|
||||
CONFIG_SPL_MMC_TINY=y
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SPL_PAYLOAD="u-boot.img"
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_SPL=y
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_DM=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_MTD=y
|
||||
# CONFIG_CMD_PINMUX is not set
|
||||
CONFIG_CMD_SPI=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_MTDIDS_DEFAULT="nor0=spi3.0"
|
||||
CONFIG_MTDPARTS_DEFAULT="spi3.0:64k(SPL),448k(uboot),128k(envs),384k(unused1),4096k(kernel),8192k(swupdate),-(unused2)"
|
||||
CONFIG_DOS_PARTITION=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx28-xea"
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent interrupts"
|
||||
CONFIG_SPL_OF_PLATDATA=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_USE_ENV_SPI_BUS=y
|
||||
CONFIG_ENV_SPI_BUS=3
|
||||
CONFIG_USE_ENV_SPI_CS=y
|
||||
CONFIG_ENV_SPI_CS=0
|
||||
CONFIG_USE_ENV_SPI_MAX_HZ=y
|
||||
CONFIG_ENV_SPI_MAX_HZ=40000000
|
||||
CONFIG_USE_ENV_SPI_MODE=y
|
||||
CONFIG_ENV_SPI_MODE=0x0
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_DEVRES=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_MXS_GPIO=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_MMC_MXS=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_DEVICE=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_BUS=3
|
||||
CONFIG_SF_DEFAULT_MODE=0x0
|
||||
CONFIG_SF_DEFAULT_SPEED=40000000
|
||||
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_ADDR_ENABLE=y
|
||||
CONFIG_PHY_ADDR=1
|
||||
CONFIG_PHY_FIXED=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_FEC_MXC=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_MXS=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_CONS_INDEX=0
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_MXS_SPI=y
|
||||
CONFIG_FS_FAT=y
|
||||
# CONFIG_SPL_OF_LIBFDT is not set
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
196
include/configs/xea.h
Normal file
196
include/configs/xea.h
Normal file
|
|
@ -0,0 +1,196 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2019 DENX Software Engineering
|
||||
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
|
||||
*
|
||||
* Copyright (C) 2018 DENX Software Engineering
|
||||
* Måns Rullgård, DENX Software Engineering, mans@mansr.com
|
||||
*
|
||||
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
|
||||
* on behalf of DENX Software Engineering GmbH
|
||||
*/
|
||||
#ifndef __CONFIGS_XEA_H__
|
||||
#define __CONFIGS_XEA_H__
|
||||
|
||||
#include <linux/sizes.h>
|
||||
|
||||
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
|
||||
|
||||
/* SPL */
|
||||
#define CONFIG_SPL_STACK 0x20000
|
||||
|
||||
#define CONFIG_SYS_SPL_ARGS_ADDR 0x44000000
|
||||
|
||||
#define CONFIG_SYS_SPI_KERNEL_OFFS SZ_1M
|
||||
#define CONFIG_SYS_SPI_ARGS_OFFS SZ_512K
|
||||
#define CONFIG_SYS_SPI_ARGS_SIZE SZ_32K
|
||||
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR (SZ_512K / 0x200)
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (SZ_32K / 0x200)
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR (SZ_1M / 0x200)
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SPI_FLASH_MTD
|
||||
#endif
|
||||
|
||||
/* Memory configuration */
|
||||
#define PHYS_SDRAM_1 0x40000000 /* Base address */
|
||||
#define PHYS_SDRAM_1_SIZE 0x10000000 /* Max 256 MB RAM */
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
|
||||
/* Environment */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/* Booting Linux */
|
||||
#define CONFIG_BOOTFILE "uImage"
|
||||
#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 "
|
||||
#define CONFIG_BOOTCOMMAND "run ${bootpri} ; run ${bootsec}"
|
||||
#define CONFIG_LOADADDR 0x42000000
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
/* Extra Environment */
|
||||
#define CONFIG_PREBOOT "run prebootcmd"
|
||||
#define CONFIG_HOSTNAME "xea"
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"bootmode=update\0" \
|
||||
"bootpri=mmc_mmc\0" \
|
||||
"bootsec=sf_swu\0" \
|
||||
"consdev=ttyAMA0\0" \
|
||||
"baudrate=115200\0" \
|
||||
"dtbaddr=0x44000000\0" \
|
||||
"dtbfile=imx28-xea.dtb\0" \
|
||||
"rootdev=/dev/mmcblk0p2\0" \
|
||||
"netdev=eth0\0" \
|
||||
"rdaddr=0x43000000\0" \
|
||||
"swufile=swupdate.img\0" \
|
||||
"sf_kernel_offset=0x100000\0" \
|
||||
"sf_kernel_size=0x400000\0" \
|
||||
"sf_swu_offset=0x500000\0" \
|
||||
"sf_swu_size=0x800000\0" \
|
||||
"rootpath=/opt/eldk-5.5/armv5te/rootfs-qte-sdk\0" \
|
||||
"do_update_mmc=" \
|
||||
"if mmc rescan ; then " \
|
||||
"mmc dev 0 ${update_mmc_part} ; " \
|
||||
"if dhcp ${hostname}/${update_filename} ; then " \
|
||||
"setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \
|
||||
"setexpr fw_sz ${fw_sz} + 1 ; " \
|
||||
"mmc write ${loadaddr} ${update_offset} ${fw_sz} ; " \
|
||||
"fi ; " \
|
||||
"fi\0" \
|
||||
"do_update_sf=" \
|
||||
"if sf probe ; then " \
|
||||
"if dhcp ${hostname}/${update_filename} ; then " \
|
||||
"sf erase ${update_offset} +${filesize} ; " \
|
||||
"sf write ${loadaddr} ${update_offset} ${filesize} ; " \
|
||||
"fi ; " \
|
||||
"fi\0" \
|
||||
"update_spl_filename=u-boot.sb\0" \
|
||||
"update_spl=" \
|
||||
"setenv update_filename ${update_spl_filename} ; " \
|
||||
"setenv update_offset 0 ; " \
|
||||
"run do_update_sf\0" \
|
||||
"update_uboot_filename=u-boot.img\0" \
|
||||
"update_uboot=" \
|
||||
"setenv update_filename ${update_uboot_filename} ; " \
|
||||
"setenv update_offset 0x10000 ; " \
|
||||
"run do_update_sf ; " \
|
||||
"setenv update_mmc_part 1 ; " \
|
||||
"setenv update_offset 0 ; " \
|
||||
"run do_update_mmc\0" \
|
||||
"update_kernel_filename=uImage\0" \
|
||||
"update_kernel=" \
|
||||
"setenv update_mmc_part 1 ; " \
|
||||
"setenv update_filename ${update_kernel_filename} ; " \
|
||||
"setenv update_offset 0x800 ; " \
|
||||
"run do_update_mmc ; " \
|
||||
"setenv update_filename ${dtbfile} ; " \
|
||||
"setenv update_offset 0x400 ; " \
|
||||
"run do_update_mmc\0" \
|
||||
"update_sfkernel=" \
|
||||
"setenv update_filename fitImage ; " \
|
||||
"setenv update_offset ${sf_kernel_offset} ; " \
|
||||
"run do_update_sf\0" \
|
||||
"update_swu=" \
|
||||
"setenv update_filename ${swufile} ; " \
|
||||
"setenv update_offset ${sf_swu_offset} ; " \
|
||||
"run do_update_sf\0" \
|
||||
"addcons=" \
|
||||
"setenv bootargs ${bootargs} " \
|
||||
"console=${consdev},${baudrate}\0" \
|
||||
"addip=" \
|
||||
"setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:" \
|
||||
"${netmask}:${hostname}:${netdev}:off\0" \
|
||||
"addmisc=" \
|
||||
"setenv bootargs ${bootargs} ${miscargs}\0" \
|
||||
"addargs=run addcons addmisc\0" \
|
||||
"mmcload=" \
|
||||
"mmc rescan ; " \
|
||||
"mmc dev 0 1 ; " \
|
||||
"mmc read ${loadaddr} 0x800 0x2000 ; " \
|
||||
"mmc read ${dtbaddr} 0x400 0x80\0" \
|
||||
"netload=" \
|
||||
"dhcp ${loadaddr} ${hostname}/${bootfile} ; " \
|
||||
"tftp ${dtbaddr} ${hostname}/${dtbfile}\0" \
|
||||
"sfload=" \
|
||||
"sf probe ; " \
|
||||
"sf read ${loadaddr} ${sf_kernel_offset} ${sf_kernel_size}\0" \
|
||||
"usbload=" \
|
||||
"usb start ; " \
|
||||
"load usb 0:1 ${loadaddr} ${bootfile}\0" \
|
||||
"miscargs=panic=1\0" \
|
||||
"mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \
|
||||
"nfsargs=" \
|
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath},v3,tcp\0" \
|
||||
"mmc_mmc=" \
|
||||
"if run mmcload mmcargs addargs ; then " \
|
||||
"bootm ${loadaddr} - ${dtbaddr} ; " \
|
||||
"fi\0" \
|
||||
"mmc_nfs=" \
|
||||
"if run mmcload nfsargs addip addargs ; then " \
|
||||
"bootm ${loadaddr} - ${dtbaddr} ; " \
|
||||
"fi\0" \
|
||||
"sf_mmc=" \
|
||||
"if run sfload mmcargs addargs ; then " \
|
||||
"bootm ${loadaddr} - ${dtbaddr} ; " \
|
||||
"fi\0" \
|
||||
"sf_swu=" \
|
||||
"if run sfload ; then " \
|
||||
"sf read ${rdaddr} ${sf_swu_offset} ${sf_swu_size} ; " \
|
||||
"setenv bootargs root=/dev/ram0 rw ; " \
|
||||
"run addargs ; " \
|
||||
"bootm ${loadaddr} ${rdaddr} ; " \
|
||||
"fi\0" \
|
||||
"net_mmc=" \
|
||||
"if run netload mmcargs addargs ; then " \
|
||||
"bootm ${loadaddr} - ${dtbaddr} ; " \
|
||||
"fi\0" \
|
||||
"net_nfs=" \
|
||||
"if run netload nfsargs addip addargs ; then " \
|
||||
"bootm ${loadaddr} - ${dtbaddr} ; " \
|
||||
"fi\0" \
|
||||
"prebootcmd=" \
|
||||
"if test \"${envsaved}\" != y ; then ; " \
|
||||
"setenv envsaved y ; " \
|
||||
"saveenv ; " \
|
||||
"fi ; " \
|
||||
"if test \"${bootmode}\" = normal ; then " \
|
||||
"setenv bootdelay 0 ; " \
|
||||
"setenv bootpri mmc_mmc ; " \
|
||||
"elif test \"${bootmode}\" = devel ; then " \
|
||||
"setenv bootdelay 3 ; " \
|
||||
"setenv bootpri net_mmc ; " \
|
||||
"else " \
|
||||
"if test \"${bootmode}\" != update ; then " \
|
||||
"echo Warning: unknown bootmode \"${bootmode}\" ; " \
|
||||
"fi ; " \
|
||||
"setenv bootdelay 1 ; " \
|
||||
"setenv bootpri sf_swu ; " \
|
||||
"fi\0"
|
||||
|
||||
/* The rest of the configuration is shared */
|
||||
#include <configs/mxs.h>
|
||||
|
||||
#endif /* __CONFIGS_XEA_H__ */
|
||||
Loading…
Reference in a new issue