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Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-marvell into next

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- pci_mvebu: Misc improvements and cleanup (Pali)
- turris_mox: Remove extra newline after module topology (Marek)
This commit is contained in:
Tom Rini 2021-12-21 08:02:28 -05:00
commit 00a4280d77
2 changed files with 13 additions and 17 deletions
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3
board/CZ.NIC/turris_mox/turris_mox.c
View file

@ -612,9 +612,6 @@ int show_board_info(void)
} }
} }
if (module_count)
printf("\n");
return 0; return 0;
} }

27
drivers/pci/pci_mvebu.c
View file

@ -14,7 +14,6 @@
#include <dm.h> #include <dm.h>
#include <log.h> #include <log.h>
#include <malloc.h> #include <malloc.h>
#include <asm/global_data.h>
#include <dm/device-internal.h> #include <dm/device-internal.h>
#include <dm/lists.h> #include <dm/lists.h>
#include <dm/of_access.h> #include <dm/of_access.h>
@ -27,8 +26,6 @@
#include <linux/ioport.h> #include <linux/ioport.h>
#include <linux/mbus.h> #include <linux/mbus.h>
DECLARE_GLOBAL_DATA_PTR;
/* PCIe unit register offsets */ /* PCIe unit register offsets */
#define SELECT(x, n) ((x >> n) & 1UL) #define SELECT(x, n) ((x >> n) & 1UL)
@ -314,7 +311,9 @@ static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
/* /*
* Setup PCIE BARs and Address Decode Wins: * Setup PCIE BARs and Address Decode Wins:
* BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks * BAR[0] -> internal registers
* BAR[1] -> covers all DRAM banks
* BAR[2] -> disabled
* WIN[0-3] -> DRAM bank[0-3] * WIN[0-3] -> DRAM bank[0-3]
*/ */
static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie) static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie)
@ -365,6 +364,10 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie)
writel(0, pcie->base + PCIE_BAR_HI_OFF(1)); writel(0, pcie->base + PCIE_BAR_HI_OFF(1));
writel(((size - 1) & 0xffff0000) | 0x1, writel(((size - 1) & 0xffff0000) | 0x1,
pcie->base + PCIE_BAR_CTRL_OFF(1)); pcie->base + PCIE_BAR_CTRL_OFF(1));
/* Setup BAR[0] to internal registers. */
writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
} }
static int mvebu_pcie_probe(struct udevice *dev) static int mvebu_pcie_probe(struct udevice *dev)
@ -445,9 +448,9 @@ static int mvebu_pcie_probe(struct udevice *dev)
if (mvebu_mbus_add_window_by_id(pcie->mem_target, pcie->mem_attr, if (mvebu_mbus_add_window_by_id(pcie->mem_target, pcie->mem_attr,
(phys_addr_t)pcie->mem.start, (phys_addr_t)pcie->mem.start,
MBUS_PCI_MEM_SIZE)) { resource_size(&pcie->mem))) {
printf("PCIe unable to add mbus window for mem at %08x+%08x\n", printf("PCIe unable to add mbus window for mem at %08x+%08x\n",
(u32)pcie->mem.start, MBUS_PCI_MEM_SIZE); (u32)pcie->mem.start, (unsigned)resource_size(&pcie->mem));
} }
pcie->io.start = (u32)mvebu_pcie_iobase; pcie->io.start = (u32)mvebu_pcie_iobase;
@ -456,9 +459,9 @@ static int mvebu_pcie_probe(struct udevice *dev)
if (mvebu_mbus_add_window_by_id(pcie->io_target, pcie->io_attr, if (mvebu_mbus_add_window_by_id(pcie->io_target, pcie->io_attr,
(phys_addr_t)pcie->io.start, (phys_addr_t)pcie->io.start,
MBUS_PCI_IO_SIZE)) { resource_size(&pcie->io))) {
printf("PCIe unable to add mbus window for IO at %08x+%08x\n", printf("PCIe unable to add mbus window for IO at %08x+%08x\n",
(u32)pcie->io.start, MBUS_PCI_IO_SIZE); (u32)pcie->io.start, (unsigned)resource_size(&pcie->io));
} }
/* Setup windows and configure host bridge */ /* Setup windows and configure host bridge */
@ -466,19 +469,15 @@ static int mvebu_pcie_probe(struct udevice *dev)
/* PCI memory space */ /* PCI memory space */
pci_set_region(hose->regions + 0, pcie->mem.start, pci_set_region(hose->regions + 0, pcie->mem.start,
pcie->mem.start, MBUS_PCI_MEM_SIZE, PCI_REGION_MEM); pcie->mem.start, resource_size(&pcie->mem), PCI_REGION_MEM);
pci_set_region(hose->regions + 1, pci_set_region(hose->regions + 1,
0, 0, 0, 0,
gd->ram_size, gd->ram_size,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
pci_set_region(hose->regions + 2, pcie->io.start, pci_set_region(hose->regions + 2, pcie->io.start,
pcie->io.start, MBUS_PCI_IO_SIZE, PCI_REGION_IO); pcie->io.start, resource_size(&pcie->io), PCI_REGION_IO);
hose->region_count = 3; hose->region_count = 3;
/* Set BAR0 to internal registers */
writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
/* PCI Bridge support 32-bit I/O and 64-bit prefetch mem addressing */ /* PCI Bridge support 32-bit I/O and 64-bit prefetch mem addressing */
pcie->cfgcache[(PCI_IO_BASE - 0x10) / 4] = pcie->cfgcache[(PCI_IO_BASE - 0x10) / 4] =
PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8); PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8);