u-boot/drivers/clk/sunxi/Makefile

#
# Copyright (C) 2018 Amarula Solutions.
#
# SPDX-License-Identifier:      GPL-2.0+
#

obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o

obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o
clk: Add Allwinner A64 CLK driver Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> 2018-12-22 16:02:49 +00:00			`#`
			`# Copyright (C) 2018 Amarula Solutions.`
			`#`
			`# SPDX-License-Identifier: GPL-2.0+`
			`#`

			`obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o`

clk: sunxi: Add Allwinner A10/A20 CLK driver Add initial clock driver for Allwinner A10/A20. - Implement USB ahb and USB clocks via ccu_clk_gate table for A10/A20, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB resets via ccu_reset table for A10/A20, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> 2018-08-02 11:22:37 +00:00			`obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o`
clk: sunxi: Add Allwinner H3/H5 CLK driver Add initial clock driver for Allwinner H3/H5. - Implement USB bus and USB clocks via ccu_clk_gate table for H3/H5, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for H3/H5, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> 2018-08-02 10:13:02 +00:00			`obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o`
clk: Add Allwinner A64 CLK driver Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> 2018-12-22 16:02:49 +00:00			`obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o`