df8e6be59a
This adds support for the RTL838x Architecture. SoCs of this type are used in managed and un-managed Switches and Routers with 8-28 ports. Drivers are provided for SoC initialization, GPIOs, Flash, Ethernet including a DSA switch driver and internal and external PHYs used with these switches. Supported SoCs: RTL8380M RTL8381M RTL8382M The kernel will also boot on the following RTL839x SoCs, however driver support apart from spi-nor is missing: RTL8390 RTL8391 RTL8393 The following PHYs are supported: RTL8214FC (Quad QSGMII multiplexing GMAC and SFP port) RTL8218B internal: internal PHY of the RTL838x chips RTL8318b external (QSGMII 8-port GMAC phy) RTL8382M SerDes for 2 SFP ports Initialization sequences for the PHYs are provided in the form of firmware files. Flash driver supports 3 / 4 byte access DSA switch driver supports VLANs, port isolation, STP and port mirroring. The ALLNET ALL-SG8208M is supported as Proof of Concept: RTL8382M SoC 1 MIPS 4KEc core @ 500MHz 8 Internal PHYs (RTL8218B) 128MB DRAM (Nanya NT5TU128MB) 16MB NOR Flash (MXIC 25L128) 8 GBEthernet ports with one green status LED each (SoC controlled) 1 Power LED (not configurable) 1 SYS LED (configurable) 1 On-Off switch (not configurable) 1 Reset button at the right behind right air-vent (not configurable) 1 Reset button on front panel (configurable) 12V 1A barrel connector 1 serial header with populated standard pin connector and with markings GND TX RX Vcc(3.3V), connection properties: 115200 8N1 To install, upload the sysupgrade image to the OEM webpage. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
111 lines
3.6 KiB
C
111 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2009 Realtek Semiconductor Corp.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef _RTL838X_SPI_H
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#define _RTL838X_SPI_H
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/*
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* Register access macros
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*/
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#define spi_r32(reg) __raw_readl(rtl838x_nor->base + reg)
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#define spi_w32(val, reg) __raw_writel(val, rtl838x_nor->base + reg)
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#define spi_w32_mask(clear, set, reg) \
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spi_w32((spi_r32(reg) & ~(clear)) | (set), reg)
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#define SPI_WAIT_READY do { \
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} while (!(spi_r32(SFCSR) & SFCSR_SPI_RDY))
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#define spi_w32w(val, reg) do { \
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__raw_writel(val, rtl838x_nor->base + reg); \
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SPI_WAIT_READY; \
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} while (0)
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#define SFCR (0x00) /*SPI Flash Configuration Register*/
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#define SFCR_CLK_DIV(val) ((val)<<29)
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#define SFCR_EnableRBO (1<<28)
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#define SFCR_EnableWBO (1<<27)
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#define SFCR_SPI_TCS(val) ((val)<<23) /*4 bit, 1111 */
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#define SFCR2 (0x04) /*For memory mapped I/O */
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#define SFCR2_SFCMD(val) ((val)<<24) /*8 bit, 1111_1111 */
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#define SFCR2_SIZE(val) ((val)<<21) /*3 bit, 111 */
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#define SFCR2_RDOPT (1<<20)
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#define SFCR2_CMDIO(val) ((val)<<18) /*2 bit, 11 */
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#define SFCR2_ADDRIO(val) ((val)<<16) /*2 bit, 11 */
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#define SFCR2_DUMMYCYCLE(val) ((val)<<13) /*3 bit, 111 */
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#define SFCR2_DATAIO(val) ((val)<<11) /*2 bit, 11 */
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#define SFCR2_HOLD_TILL_SFDR2 (1<<10)
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#define SFCR2_GETSIZE(x) (((x)&0x00E00000)>>21)
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#define SFCSR (0x08) /*SPI Flash Control&Status Register*/
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#define SFCSR_SPI_CSB0 (1<<31)
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#define SFCSR_SPI_CSB1 (1<<30)
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#define SFCSR_LEN(val) ((val)<<28) /*2 bits*/
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#define SFCSR_SPI_RDY (1<<27)
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#define SFCSR_IO_WIDTH(val) ((val)<<25) /*2 bits*/
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#define SFCSR_CHIP_SEL (1<<24)
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#define SFCSR_CMD_BYTE(val) ((val)<<16) /*8 bit, 1111_1111 */
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#define SFDR (0x0C) /*SPI Flash Data Register*/
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#define SFDR2 (0x10) /*SPI Flash Data Register - for post SPI bootup setting*/
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#define SPI_CS_INIT (SFCSR_SPI_CSB0 | SFCSR_SPI_CSB1 | SPI_LEN1)
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#define SPI_CS0 SFCSR_SPI_CSB0
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#define SPI_CS1 SFCSR_SPI_CSB1
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#define SPI_eCS0 ((SFCSR_SPI_CSB1)) /*and SFCSR to active CS0*/
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#define SPI_eCS1 ((SFCSR_SPI_CSB0)) /*and SFCSR to active CS1*/
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#define SPI_WIP (1) /* Write In Progress */
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#define SPI_WEL (1<<1) /* Write Enable Latch*/
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#define SPI_SST_QIO_WIP (1<<7) /* SST QIO Flash Write In Progress */
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#define SPI_LEN_INIT 0xCFFFFFFF /* and SFCSR to init */
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#define SPI_LEN4 0x30000000 /* or SFCSR to set */
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#define SPI_LEN3 0x20000000 /* or SFCSR to set */
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#define SPI_LEN2 0x10000000 /* or SFCSR to set */
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#define SPI_LEN1 0x00000000 /* or SFCSR to set */
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#define SPI_SETLEN(val) do { \
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SPI_REG(SFCSR) &= 0xCFFFFFFF; \
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SPI_REG(SFCSR) |= (val-1)<<28; \
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} while (0)
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/*
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* SPI interface control
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*/
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#define RTL8390_SOC_SPI_MMIO_CONF (0x04)
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#define IOSTATUS_CIO_MASK (0x00000038)
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/* Chip select: bits 4-7*/
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#define CS0 (1<<4)
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#define R_MODE 0x04
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/* io_status */
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#define IO1 (1<<0)
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#define IO2 (1<<1)
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#define CIO1 (1<<3)
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#define CIO2 (1<<4)
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#define CMD_IO1 (1<<6)
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#define W_ADDR_IO1 ((1)<<12)
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#define R_ADDR_IO2 ((2)<<9)
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#define R_DATA_IO2 ((2)<<15)
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#define W_DATA_IO1 ((1)<<18)
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/* Commands */
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#define SPI_C_RSTQIO 0xFF
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#define SPI_MAX_TRANSFER_SIZE 256
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#endif /* _RTL838X_SPI_H */
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