moves extraction entries out of 11-ath10k-caldata and into the individual board's device-tree. Some notes: - mmc could work as well (not tested) - devices that pass the partitions via mtdparts bootargs are kept as is - gl-b2200 has a weird pcie wifi device (vendor claims 9886 wave 2. But firmware-extraction was for a wave 1 device?!) Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
371 lines
5.9 KiB
Text
371 lines
5.9 KiB
Text
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
|
|
|
#include "qcom-ipq4019.dtsi"
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/input/input.h>
|
|
#include <dt-bindings/soc/qcom,tcsr.h>
|
|
|
|
/ {
|
|
model = "GL.iNet GL-S1300";
|
|
compatible = "glinet,gl-s1300";
|
|
|
|
aliases {
|
|
led-boot = &led_power;
|
|
led-failsafe = &led_power;
|
|
led-running = &led_power;
|
|
led-upgrade = &led_power;
|
|
};
|
|
|
|
memory {
|
|
device_type = "memory";
|
|
reg = <0x80000000 0x10000000>;
|
|
};
|
|
|
|
soc {
|
|
rng@22000 {
|
|
status = "okay";
|
|
};
|
|
|
|
mdio@90000 {
|
|
status = "okay";
|
|
};
|
|
|
|
ess-psgmii@98000 {
|
|
status = "okay";
|
|
};
|
|
|
|
tcsr@1949000 {
|
|
compatible = "qcom,tcsr";
|
|
reg = <0x1949000 0x100>;
|
|
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
|
};
|
|
|
|
tcsr@194b000 {
|
|
/* select hostmode */
|
|
compatible = "qcom,tcsr";
|
|
reg = <0x194b000 0x100>;
|
|
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
|
|
status = "okay";
|
|
};
|
|
|
|
ess_tcsr@1953000 {
|
|
compatible = "qcom,tcsr";
|
|
reg = <0x1953000 0x1000>;
|
|
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
|
};
|
|
|
|
tcsr@1957000 {
|
|
compatible = "qcom,tcsr";
|
|
reg = <0x1957000 0x100>;
|
|
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
|
};
|
|
|
|
usb2@60f8800 {
|
|
status = "okay";
|
|
};
|
|
|
|
usb3@8af8800 {
|
|
status = "okay";
|
|
};
|
|
|
|
crypto@8e3a000 {
|
|
status = "okay";
|
|
};
|
|
|
|
watchdog@b017000 {
|
|
status = "okay";
|
|
};
|
|
|
|
ess-switch@c000000 {
|
|
status = "okay";
|
|
switch_lan_bmp = <0x18>;
|
|
switch_wan_bmp = <0x20>;
|
|
};
|
|
|
|
edma@c080000 {
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
keys {
|
|
compatible = "gpio-keys";
|
|
|
|
wps {
|
|
label = "wps";
|
|
gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
|
|
linux,code = <KEY_WPS_BUTTON>;
|
|
};
|
|
|
|
reset {
|
|
label = "reset";
|
|
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
|
|
linux,code = <KEY_RESTART>;
|
|
};
|
|
};
|
|
|
|
leds {
|
|
compatible = "gpio-leds";
|
|
|
|
led_power: power {
|
|
label = "green:power";
|
|
gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
|
|
default-state = "on";
|
|
};
|
|
|
|
mesh {
|
|
label = "green:mesh";
|
|
gpios = <&tlmm 59 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
wlan {
|
|
label = "green:wlan";
|
|
gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;
|
|
linux,default-trigger = "phy0tpt";
|
|
};
|
|
};
|
|
};
|
|
|
|
&vqmmc {
|
|
status = "okay";
|
|
};
|
|
|
|
&sdhci {
|
|
status = "okay";
|
|
pinctrl-0 = <&sd_pins>;
|
|
pinctrl-names = "default";
|
|
cd-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
|
|
vqmmc-supply = <&vqmmc>;
|
|
};
|
|
|
|
&blsp_dma {
|
|
status = "okay";
|
|
};
|
|
|
|
&cryptobam {
|
|
status = "okay";
|
|
};
|
|
|
|
&blsp1_spi1 {
|
|
pinctrl-0 = <&spi_0_pins>;
|
|
pinctrl-names = "default";
|
|
status = "okay";
|
|
cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
|
|
|
|
flash@0 {
|
|
compatible = "jedec,spi-nor";
|
|
reg = <0>;
|
|
spi-max-frequency = <24000000>;
|
|
|
|
partitions {
|
|
compatible = "fixed-partitions";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
SBL1@0 {
|
|
label = "SBL1";
|
|
reg = <0x0 0x40000>;
|
|
read-only;
|
|
};
|
|
|
|
MIBIB@40000 {
|
|
label = "MIBIB";
|
|
reg = <0x40000 0x20000>;
|
|
read-only;
|
|
};
|
|
|
|
QSEE@60000 {
|
|
label = "QSEE";
|
|
reg = <0x60000 0x60000>;
|
|
read-only;
|
|
};
|
|
|
|
CDT@c0000 {
|
|
label = "CDT";
|
|
reg = <0xc0000 0x10000>;
|
|
read-only;
|
|
};
|
|
|
|
DDRPARAMS@d0000 {
|
|
label = "DDRPARAMS";
|
|
reg = <0xd0000 0x10000>;
|
|
read-only;
|
|
};
|
|
|
|
APPSBLENV@e0000 {
|
|
label = "APPSBLENV";
|
|
reg = <0xe0000 0x10000>;
|
|
read-only;
|
|
};
|
|
|
|
APPSBL@f0000 {
|
|
label = "APPSBL";
|
|
reg = <0xf0000 0x80000>;
|
|
read-only;
|
|
};
|
|
|
|
ART@170000 {
|
|
label = "ART";
|
|
reg = <0x170000 0x10000>;
|
|
read-only;
|
|
compatible = "nvmem-cells";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
precal_art_1000: precal@1000 {
|
|
reg = <0x1000 0x2f20>;
|
|
};
|
|
|
|
precal_art_5000: precal@5000 {
|
|
reg = <0x5000 0x2f20>;
|
|
};
|
|
};
|
|
|
|
firmware@180000 {
|
|
compatible = "denx,fit";
|
|
label = "firmware";
|
|
reg = <0x180000 0xe80000>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&blsp1_spi2 {
|
|
pinctrl-0 = <&spi_1_pins>;
|
|
pinctrl-names = "default";
|
|
status = "okay";
|
|
|
|
spidev1: spi@0 {
|
|
compatible = "siliconlabs,si3210";
|
|
reg = <0>;
|
|
spi-max-frequency = <24000000>;
|
|
};
|
|
};
|
|
|
|
&blsp1_uart1 {
|
|
pinctrl-0 = <&serial_pins>;
|
|
pinctrl-names = "default";
|
|
status = "okay";
|
|
};
|
|
|
|
&blsp1_uart2 {
|
|
pinctrl-0 = <&serial_1_pins>;
|
|
pinctrl-names = "default";
|
|
status = "okay";
|
|
};
|
|
|
|
&tlmm {
|
|
serial_pins: serial_pinmux {
|
|
mux {
|
|
pins = "gpio16", "gpio17";
|
|
function = "blsp_uart0";
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
serial_1_pins: serial1_pinmux {
|
|
mux {
|
|
pins = "gpio8", "gpio9",
|
|
"gpio10", "gpio11";
|
|
function = "blsp_uart1";
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
spi_0_pins: spi_0_pinmux {
|
|
pinmux {
|
|
function = "blsp_spi0";
|
|
pins = "gpio13", "gpio14", "gpio15";
|
|
};
|
|
pinmux_cs {
|
|
function = "gpio";
|
|
pins = "gpio12";
|
|
};
|
|
pinconf {
|
|
pins = "gpio13", "gpio14", "gpio15";
|
|
drive-strength = <12>;
|
|
bias-disable;
|
|
};
|
|
pinconf_cs {
|
|
pins = "gpio12";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
output-high;
|
|
};
|
|
};
|
|
|
|
spi_1_pins: spi_1_pinmux {
|
|
mux {
|
|
pins = "gpio44", "gpio46", "gpio47";
|
|
function = "blsp_spi1";
|
|
bias-disable;
|
|
};
|
|
host_int {
|
|
pins = "gpio42";
|
|
function = "gpio";
|
|
input;
|
|
};
|
|
cs {
|
|
pins = "gpio45";
|
|
function = "gpio";
|
|
bias-pull-up;
|
|
};
|
|
wake {
|
|
pins = "gpio40";
|
|
function = "gpio";
|
|
output-high;
|
|
};
|
|
reset {
|
|
pins = "gpio49";
|
|
function = "gpio";
|
|
output-high;
|
|
};
|
|
};
|
|
|
|
sd_pins: sd_pins {
|
|
pinmux {
|
|
function = "sdio";
|
|
pins = "gpio23", "gpio24", "gpio25", "gpio26",
|
|
"gpio28", "gpio29", "gpio30", "gpio31";
|
|
drive-strength = <10>;
|
|
};
|
|
|
|
pinmux_sd_clk {
|
|
function = "sdio";
|
|
pins = "gpio27";
|
|
drive-strength = <16>;
|
|
};
|
|
|
|
pinmux_sd7 {
|
|
function = "sdio";
|
|
pins = "gpio32";
|
|
drive-strength = <10>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
&usb2_hs_phy {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb3_hs_phy {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb3_ss_phy {
|
|
status = "okay";
|
|
};
|
|
|
|
&wifi0 {
|
|
status = "okay";
|
|
nvmem-cell-names = "pre-calibration";
|
|
nvmem-cells = <&precal_art_1000>;
|
|
qcom,ath10k-calibration-variant = "GL-S1300";
|
|
};
|
|
|
|
&wifi1 {
|
|
status = "okay";
|
|
nvmem-cell-names = "pre-calibration";
|
|
nvmem-cells = <&precal_art_5000>;
|
|
qcom,ath10k-calibration-variant = "GL-S1300";
|
|
};
|