dc9cc0d3e2
This adds support for identifying QoS information in packets and use this and rate control information to submit to multiple egress queues. The ethernet driver is also made to support 2 egress and up to 32 egress queues. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
513 lines
13 KiB
C
513 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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#include <asm/mach-rtl838x/mach-rtl83xx.h>
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#include "rtl83xx.h"
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extern struct mutex smi_lock;
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extern struct rtl83xx_soc_info soc_info;
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void rtl839x_print_matrix(void)
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{
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volatile u64 *ptr9;
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int i;
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ptr9 = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0);
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for (i = 0; i < 52; i += 4)
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pr_debug("> %16llx %16llx %16llx %16llx\n",
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ptr9[i + 0], ptr9[i + 1], ptr9[i + 2], ptr9[i + 3]);
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pr_debug("CPU_PORT> %16llx\n", ptr9[52]);
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}
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static inline int rtl839x_port_iso_ctrl(int p)
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{
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return RTL839X_PORT_ISO_CTRL(p);
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}
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static inline void rtl839x_exec_tbl0_cmd(u32 cmd)
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{
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sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_0);
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do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_0) & BIT(16));
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}
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static inline void rtl839x_exec_tbl1_cmd(u32 cmd)
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{
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sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_1);
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do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_1) & BIT(16));
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}
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inline void rtl839x_exec_tbl2_cmd(u32 cmd)
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{
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sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_2);
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do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_2) & (1 << 9));
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}
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static inline int rtl839x_tbl_access_data_0(int i)
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{
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return RTL839X_TBL_ACCESS_DATA_0(i);
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}
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static void rtl839x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
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{
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u32 cmd;
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u64 v;
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u32 u, w;
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cmd = 1 << 16 /* Execute cmd */
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| 0 << 15 /* Read */
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| 0 << 12 /* Table type 0b000 */
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| (vlan & 0xfff);
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rtl839x_exec_tbl0_cmd(cmd);
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v = sw_r32(RTL839X_TBL_ACCESS_DATA_0(0));
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v <<= 32;
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u = sw_r32(RTL839X_TBL_ACCESS_DATA_0(1));
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v |= u;
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info->tagged_ports = v >> 11;
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w = sw_r32(RTL839X_TBL_ACCESS_DATA_0(2));
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info->profile_id = w >> 30 | ((u & 1) << 2);
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info->hash_mc_fid = !!(u & 2);
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info->hash_uc_fid = !!(u & 4);
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info->fid = (u >> 3) & 0xff;
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cmd = 1 << 15 /* Execute cmd */
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| 0 << 14 /* Read */
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| 0 << 12 /* Table type 0b00 */
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| (vlan & 0xfff);
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rtl839x_exec_tbl1_cmd(cmd);
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v = sw_r32(RTL839X_TBL_ACCESS_DATA_1(0));
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v <<= 32;
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v |= sw_r32(RTL839X_TBL_ACCESS_DATA_1(1));
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info->untagged_ports = v >> 11;
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}
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static void rtl839x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
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{
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u32 cmd = BIT(16) /* Execute cmd */
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| BIT(15) /* Write */
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| 0 << 12 /* Table type 0b00 */
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| (vlan & 0xfff);
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u32 w;
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u64 v = info->tagged_ports << 11;
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v |= info->profile_id >> 2;
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v |= info->hash_mc_fid ? 2 : 0;
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v |= info->hash_uc_fid ? 4 : 0;
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v |= ((u32)info->fid) << 3;
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rtl839x_set_port_reg_be(v, RTL838X_TBL_ACCESS_DATA_0(0));
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w = info->profile_id;
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sw_w32(w << 30, RTL838X_TBL_ACCESS_DATA_0(2));
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rtl839x_exec_tbl0_cmd(cmd);
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}
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static void rtl839x_vlan_set_untagged(u32 vlan, u64 portmask)
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{
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u32 cmd = BIT(16) /* Execute cmd */
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| BIT(15) /* Write */
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| 0 << 12 /* Table type 0b00 */
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| (vlan & 0xfff);
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rtl839x_set_port_reg_be(portmask << 11, RTL838X_TBL_ACCESS_DATA_1(0));
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rtl839x_exec_tbl1_cmd(cmd);
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}
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static inline int rtl839x_mac_force_mode_ctrl(int p)
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{
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return RTL839X_MAC_FORCE_MODE_CTRL + (p << 2);
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}
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static inline int rtl839x_mac_port_ctrl(int p)
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{
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return RTL839X_MAC_PORT_CTRL(p);
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}
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static inline int rtl839x_l2_port_new_salrn(int p)
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{
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return RTL839X_L2_PORT_NEW_SALRN(p);
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}
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static inline int rtl839x_l2_port_new_sa_fwd(int p)
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{
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return RTL839X_L2_PORT_NEW_SA_FWD(p);
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}
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static inline int rtl839x_mac_link_spd_sts(int p)
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{
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return RTL839X_MAC_LINK_SPD_STS(p);
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}
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static inline int rtl839x_trk_mbr_ctr(int group)
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{
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return RTL839X_TRK_MBR_CTR + (group << 3);
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}
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static void rtl839x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e)
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{
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/* Table contains different entry types, we need to identify the right one:
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* Check for MC entries, first
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*/
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e->is_ip_mc = !!(r[2] & BIT(31));
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e->is_ipv6_mc = !!(r[2] & BIT(30));
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e->type = L2_INVALID;
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if (!e->is_ip_mc) {
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e->mac[0] = (r[0] >> 12);
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e->mac[1] = (r[0] >> 4);
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e->mac[2] = ((r[1] >> 28) | (r[0] << 4));
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e->mac[3] = (r[1] >> 20);
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e->mac[4] = (r[1] >> 12);
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e->mac[5] = (r[1] >> 4);
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/* Is it a unicast entry? check multicast bit */
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if (!(e->mac[0] & 1)) {
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e->is_static = !!((r[2] >> 18) & 1);
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e->vid = (r[2] >> 4) & 0xfff;
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e->rvid = (r[0] >> 20) & 0xfff;
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e->port = (r[2] >> 24) & 0x3f;
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e->block_da = !!(r[2] & (1 << 19));
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e->block_sa = !!(r[2] & (1 << 20));
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e->suspended = !!(r[2] & (1 << 17));
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e->next_hop = !!(r[2] & (1 << 16));
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if (e->next_hop)
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pr_info("Found next hop entry, need to read data\n");
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e->age = (r[2] >> 21) & 3;
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e->valid = true;
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if (!(r[2] & 0xc0fd0000)) /* Check for valid entry */
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e->valid = false;
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else
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e->type = L2_UNICAST;
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} else {
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e->valid = true;
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e->type = L2_MULTICAST;
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e->mc_portmask_index = (r[2]>>6) & 0xfff;
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}
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}
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if (e->is_ip_mc) {
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e->valid = true;
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e->type = IP4_MULTICAST;
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}
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if (e->is_ipv6_mc) {
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e->valid = true;
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e->type = IP6_MULTICAST;
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}
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}
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static u64 rtl839x_read_l2_entry_using_hash(u32 hash, u32 position, struct rtl838x_l2_entry *e)
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{
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u64 entry;
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u32 r[3];
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/* Search in SRAM, with hash and at position in hash bucket (0-3) */
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u32 idx = (0 << 14) | (hash << 2) | position;
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u32 cmd = 1 << 17 /* Execute cmd */
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| 0 << 16 /* Read */
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| 0 << 14 /* Table type 0b00 */
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| (idx & 0x3fff);
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sw_w32(cmd, RTL839X_TBL_ACCESS_L2_CTRL);
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do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & (1 << 17));
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r[0] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(0));
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r[1] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(1));
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r[2] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(2));
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rtl839x_fill_l2_entry(r, e);
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entry = (((u64) r[0]) << 12) | ((r[1] & 0xfffffff0) << 12) | ((r[2] >> 4) & 0xfff);
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return entry;
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}
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static u64 rtl839x_read_cam(int idx, struct rtl838x_l2_entry *e)
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{
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u64 entry;
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u32 r[3];
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u32 cmd = 1 << 17 /* Execute cmd */
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| 0 << 16 /* Read */
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| 1 << 14 /* Table type 0b01 */
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| (idx & 0x3f);
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sw_w32(cmd, RTL839X_TBL_ACCESS_L2_CTRL);
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do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & (1 << 17));
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r[0] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(0));
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r[1] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(1));
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r[2] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(2));
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rtl839x_fill_l2_entry(r, e);
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if (e->valid)
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pr_info("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
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else
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return 0;
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entry = (((u64) r[0]) << 12) | ((r[1] & 0xfffffff0) << 12) | ((r[2] >> 4) & 0xfff);
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return entry;
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}
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static inline int rtl839x_vlan_profile(int profile)
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{
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return RTL839X_VLAN_PROFILE(profile);
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}
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static inline int rtl839x_vlan_port_egr_filter(int port)
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{
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return RTL839X_VLAN_PORT_EGR_FLTR(port);
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}
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static inline int rtl839x_vlan_port_igr_filter(int port)
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{
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return RTL839X_VLAN_PORT_IGR_FLTR(port);
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}
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u64 rtl839x_traffic_get(int source)
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{
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return rtl839x_get_port_reg_be(rtl839x_port_iso_ctrl(source));
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}
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void rtl839x_traffic_set(int source, u64 dest_matrix)
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{
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rtl839x_set_port_reg_be(dest_matrix, rtl839x_port_iso_ctrl(source));
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}
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void rtl839x_traffic_enable(int source, int dest)
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{
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rtl839x_mask_port_reg_be(0, BIT_ULL(dest), rtl839x_port_iso_ctrl(source));
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}
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void rtl839x_traffic_disable(int source, int dest)
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{
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rtl839x_mask_port_reg_be(BIT(dest), 0, rtl839x_port_iso_ctrl(source));
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}
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irqreturn_t rtl839x_switch_irq(int irq, void *dev_id)
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{
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struct dsa_switch *ds = dev_id;
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u32 status = sw_r32(RTL839X_ISR_GLB_SRC);
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u64 ports = rtl839x_get_port_reg_le(RTL839X_ISR_PORT_LINK_STS_CHG);
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u64 link;
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int i;
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/* Clear status */
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rtl839x_set_port_reg_le(ports, RTL839X_ISR_PORT_LINK_STS_CHG);
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pr_debug("RTL8390 Link change: status: %x, ports %llx\n", status, ports);
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for (i = 0; i < 52; i++) {
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if (ports & (1ULL << i)) {
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link = rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS);
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if (link & (1ULL << i))
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dsa_port_phylink_mac_change(ds, i, true);
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else
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dsa_port_phylink_mac_change(ds, i, false);
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}
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}
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return IRQ_HANDLED;
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}
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// TODO: unused
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int rtl8390_sds_power(int mac, int val)
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{
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u32 offset = (mac == 48) ? 0x0 : 0x100;
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u32 mode = val ? 0 : 1;
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pr_debug("In %s: mac %d, set %d\n", __func__, mac, val);
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if ((mac != 48) && (mac != 49)) {
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pr_err("%s: not an SFP port: %d\n", __func__, mac);
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return -1;
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}
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// Set bit 1003. 1000 starts at 7c
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sw_w32_mask(BIT(11), mode << 11, RTL839X_SDS12_13_PWR0 + offset);
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return 0;
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}
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int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
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{
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u32 v;
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if (port > 63 || page > 4095 || reg > 31)
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return -ENOTSUPP;
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mutex_lock(&smi_lock);
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sw_w32_mask(0xffff0000, port << 16, RTL839X_PHYREG_DATA_CTRL);
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v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
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sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
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sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
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v |= 1;
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sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
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do {
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} while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1);
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*val = sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff;
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mutex_unlock(&smi_lock);
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return 0;
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}
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int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val)
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{
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u32 v;
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int err = 0;
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val &= 0xffff;
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if (port > 63 || page > 4095 || reg > 31)
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return -ENOTSUPP;
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mutex_lock(&smi_lock);
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/* Clear both port registers */
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sw_w32(0, RTL839X_PHYREG_PORT_CTRL(0));
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sw_w32(0, RTL839X_PHYREG_PORT_CTRL(0) + 4);
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sw_w32_mask(0, BIT(port), RTL839X_PHYREG_PORT_CTRL(port));
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sw_w32_mask(0xffff0000, val << 16, RTL839X_PHYREG_DATA_CTRL);
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v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
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sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
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sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
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v |= BIT(3) | 1; /* Write operation and execute */
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sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
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do {
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} while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1);
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if (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x2)
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err = -EIO;
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mutex_unlock(&smi_lock);
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return err;
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}
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void rtl8390_get_version(struct rtl838x_switch_priv *priv)
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{
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u32 info;
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sw_w32_mask(0xf << 28, 0xa << 28, RTL839X_CHIP_INFO);
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info = sw_r32(RTL839X_CHIP_INFO);
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pr_debug("Chip-Info: %x\n", info);
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priv->version = RTL8390_VERSION_A;
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}
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u32 rtl839x_hash(struct rtl838x_switch_priv *priv, u64 seed)
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{
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u32 h1, h2, h;
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if (sw_r32(priv->r->l2_ctrl_0) & 1) {
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h1 = (u32) (((seed >> 60) & 0x3f) ^ ((seed >> 54) & 0x3f)
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^ ((seed >> 36) & 0x3f) ^ ((seed >> 30) & 0x3f)
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^ ((seed >> 12) & 0x3f) ^ ((seed >> 6) & 0x3f));
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h2 = (u32) (((seed >> 48) & 0x3f) ^ ((seed >> 42) & 0x3f)
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^ ((seed >> 24) & 0x3f) ^ ((seed >> 18) & 0x3f)
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^ (seed & 0x3f));
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h = (h1 << 6) | h2;
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} else {
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h = (seed >> 60)
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^ ((((seed >> 48) & 0x3f) << 6) | ((seed >> 54) & 0x3f))
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^ ((seed >> 36) & 0xfff) ^ ((seed >> 24) & 0xfff)
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^ ((seed >> 12) & 0xfff) ^ (seed & 0xfff);
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}
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return h;
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}
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void rtl839x_vlan_profile_dump(int index)
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{
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u32 profile, profile1;
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if (index < 0 || index > 7)
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return;
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profile1 = sw_r32(RTL839X_VLAN_PROFILE(index) + 4);
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profile = sw_r32(RTL839X_VLAN_PROFILE(index));
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pr_debug("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %x, \
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IPv4 Unknown MultiCast Field %x, IPv6 Unknown MultiCast Field: %x",
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index, profile & 1, (profile >> 1) & 0xfff, (profile >> 13) & 0xfff,
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(profile1) & 0xfff);
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}
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static void rtl839x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
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{
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int i;
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u32 cmd = 1 << 16 /* Execute cmd */
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| 0 << 15 /* Read */
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| 5 << 12 /* Table type 0b101 */
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| (msti & 0xfff);
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priv->r->exec_tbl0_cmd(cmd);
|
|
|
|
for (i = 0; i < 4; i++)
|
|
port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
|
|
}
|
|
|
|
static void rtl839x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
|
|
{
|
|
int i;
|
|
u32 cmd = 1 << 16 /* Execute cmd */
|
|
| 1 << 15 /* Write */
|
|
| 5 << 12 /* Table type 0b101 */
|
|
| (msti & 0xfff);
|
|
for (i = 0; i < 4; i++)
|
|
sw_w32(port_state[i], priv->r->tbl_access_data_0(i));
|
|
priv->r->exec_tbl0_cmd(cmd);
|
|
}
|
|
|
|
const struct rtl838x_reg rtl839x_reg = {
|
|
.mask_port_reg_be = rtl839x_mask_port_reg_be,
|
|
.set_port_reg_be = rtl839x_set_port_reg_be,
|
|
.get_port_reg_be = rtl839x_get_port_reg_be,
|
|
.mask_port_reg_le = rtl839x_mask_port_reg_le,
|
|
.set_port_reg_le = rtl839x_set_port_reg_le,
|
|
.get_port_reg_le = rtl839x_get_port_reg_le,
|
|
.stat_port_rst = RTL839X_STAT_PORT_RST,
|
|
.stat_rst = RTL839X_STAT_RST,
|
|
.stat_port_std_mib = RTL839X_STAT_PORT_STD_MIB,
|
|
.traffic_enable = rtl839x_traffic_enable,
|
|
.traffic_disable = rtl839x_traffic_disable,
|
|
.traffic_get = rtl839x_traffic_get,
|
|
.traffic_set = rtl839x_traffic_set,
|
|
.port_iso_ctrl = rtl839x_port_iso_ctrl,
|
|
.l2_ctrl_0 = RTL839X_L2_CTRL_0,
|
|
.l2_ctrl_1 = RTL839X_L2_CTRL_1,
|
|
.l2_port_aging_out = RTL839X_L2_PORT_AGING_OUT,
|
|
.smi_poll_ctrl = RTL839X_SMI_PORT_POLLING_CTRL,
|
|
.l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
|
|
.exec_tbl0_cmd = rtl839x_exec_tbl0_cmd,
|
|
.exec_tbl1_cmd = rtl839x_exec_tbl1_cmd,
|
|
.tbl_access_data_0 = rtl839x_tbl_access_data_0,
|
|
.isr_glb_src = RTL839X_ISR_GLB_SRC,
|
|
.isr_port_link_sts_chg = RTL839X_ISR_PORT_LINK_STS_CHG,
|
|
.imr_port_link_sts_chg = RTL839X_IMR_PORT_LINK_STS_CHG,
|
|
.imr_glb = RTL839X_IMR_GLB,
|
|
.vlan_tables_read = rtl839x_vlan_tables_read,
|
|
.vlan_set_tagged = rtl839x_vlan_set_tagged,
|
|
.vlan_set_untagged = rtl839x_vlan_set_untagged,
|
|
.vlan_profile_dump = rtl839x_vlan_profile_dump,
|
|
.stp_get = rtl839x_stp_get,
|
|
.stp_set = rtl839x_stp_set,
|
|
.mac_force_mode_ctrl = rtl839x_mac_force_mode_ctrl,
|
|
.mac_port_ctrl = rtl839x_mac_port_ctrl,
|
|
.l2_port_new_salrn = rtl839x_l2_port_new_salrn,
|
|
.l2_port_new_sa_fwd = rtl839x_l2_port_new_sa_fwd,
|
|
.mir_ctrl = RTL839X_MIR_CTRL,
|
|
.mir_dpm = RTL839X_MIR_DPM_CTRL,
|
|
.mir_spm = RTL839X_MIR_SPM_CTRL,
|
|
.mac_link_sts = RTL839X_MAC_LINK_STS,
|
|
.mac_link_dup_sts = RTL839X_MAC_LINK_DUP_STS,
|
|
.mac_link_spd_sts = rtl839x_mac_link_spd_sts,
|
|
.mac_rx_pause_sts = RTL839X_MAC_RX_PAUSE_STS,
|
|
.mac_tx_pause_sts = RTL839X_MAC_TX_PAUSE_STS,
|
|
.read_l2_entry_using_hash = rtl839x_read_l2_entry_using_hash,
|
|
.read_cam = rtl839x_read_cam,
|
|
.vlan_port_egr_filter = RTL839X_VLAN_PORT_EGR_FLTR(0),
|
|
.vlan_port_igr_filter = RTL839X_VLAN_PORT_IGR_FLTR(0),
|
|
.vlan_port_pb = RTL839X_VLAN_PORT_PB_VLAN,
|
|
.vlan_port_tag_sts_ctrl = RTL839X_VLAN_PORT_TAG_STS_CTRL,
|
|
.trk_mbr_ctr = rtl839x_trk_mbr_ctr,
|
|
.rma_bpdu_fld_pmask = RTL839X_RMA_BPDU_FLD_PMSK,
|
|
.spcl_trap_eapol_ctrl = RTL839X_SPCL_TRAP_EAPOL_CTRL,
|
|
};
|