58d2bd88ae
Changes:
- Update patches
- Update dts with new binding
Tx term offset dropped and replaced with a new compatible
Removed:
- 0071-5-PCI-qcom-Programming-the-PCIE-iATU-for-IPQ806x
Pci init does the same exact thing (was needed in older kernel version)
- 0071-7-pcie-Set-PCIE-MRRS-and-MPS-to-256B
Rejected upstream, can't find any reason to have this. No regression with
testing it on R7800.
Tested on R7800 (ipq8065), R7500 v2 ("ipq8064-v2")
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Tested-by: Paul Blazejowski <paulb@blazebox.homeip.net> [R7800]
[rebase and refresh]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
69 lines
969 B
Text
69 lines
969 B
Text
#include "qcom-ipq8064.dtsi"
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/ {
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aliases {
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serial0 = &gsbi4_serial;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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rsvd@41200000 {
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reg = <0x41200000 0x300000>;
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no-map;
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};
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};
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};
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&gsbi4 {
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qcom,mode = <GSBI_PROT_I2C_UART>;
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status = "okay";
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serial@16340000 {
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status = "okay";
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};
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/*
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* The i2c device on gsbi4 should not be enabled.
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* On ipq806x designs gsbi4 i2c is meant for exclusive
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* RPM usage. Turning this on in kernel manifests as
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* i2c failure for the RPM.
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*/
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};
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&CPU_SPC {
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status = "okay";
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};
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&pcie0 {
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compatible = "qcom,pcie-ipq8064-v2";
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};
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&pcie1 {
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compatible = "qcom,pcie-ipq8064-v2";
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};
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&pcie2 {
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compatible = "qcom,pcie-ipq8064-v2";
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};
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&sata {
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ports-implemented = <0x1>;
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};
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&ss_phy_0 {
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qcom,rx-eq = <2>;
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qcom,tx-deamp_3_5db = <32>;
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qcom,mpll = <5>;
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};
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&ss_phy_1 {
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qcom,rx-eq = <2>;
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qcom,tx-deamp_3_5db = <32>;
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qcom,mpll = <5>;
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};
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