3a187fa718
Also add a new kconfig symbol (CONFIG_KCMP) to the generic config, disabling the SYS_kcmp syscall (it was split from CONFIG_CHECKPOINT_RESTORE, which is disabled by default, so the previous behaviour is kept). Removed (upstreamed) patches: 070-net-icmp-pass-zeroed-opts-from-icmp-v6-_ndo_send-bef.patch 081-wireguard-device-do-not-generate-ICMP-for-non-IP-pac.patch 082-wireguard-queueing-get-rid-of-per-peer-ring-buffers.patch 083-wireguard-kconfig-use-arm-chacha-even-with-no-neon.patch 830-v5.12-0002-usb-serial-option-update-interface-mapping-for-ZTE-P685M.patch Manually rebased patches: 313-helios4-dts-status-led-alias.patch 104-powerpc-mpc85xx-change-P2020RDB-dts-file-for-OpenWRT.patch Run tested: ath79 (TL-WDR3600) mvebu (Turris Omnia) Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
85 lines
2.5 KiB
Diff
85 lines
2.5 KiB
Diff
From: Felix Fietkau <nbd@nbd.name>
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Date: Fri, 4 Sep 2020 18:36:06 +0200
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Subject: [PATCH] net: ethernet: mtk_eth_soc: add support for coherent DMA
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It improves performance by eliminating the need for a cache flush on rx and tx
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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---
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--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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@@ -357,7 +357,7 @@
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};
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cci_control2: slave-if@5000 {
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- compatible = "arm,cci-400-ctrl-if";
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+ compatible = "arm,cci-400-ctrl-if", "syscon";
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interface-type = "ace";
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reg = <0x5000 0x1000>;
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};
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@@ -969,6 +969,8 @@
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power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
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mediatek,ethsys = <ðsys>;
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mediatek,sgmiisys = <&sgmiisys>;
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+ mediatek,cci-control = <&cci_control2>;
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+ dma-coherent;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -9,6 +9,7 @@
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#include <linux/of_device.h>
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#include <linux/of_mdio.h>
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#include <linux/of_net.h>
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+#include <linux/of_address.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include <linux/clk.h>
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@@ -2482,6 +2483,13 @@ static int mtk_hw_init(struct mtk_eth *e
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if (ret)
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goto err_disable_pm;
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+ if (of_dma_is_coherent(eth->dev->of_node)) {
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+ u32 mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |
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+ ETHSYS_DMA_AG_MAP_PPE;
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+
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+ regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, mask, mask);
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+ }
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+
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
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ret = device_reset(eth->dev);
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if (ret) {
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@@ -3061,6 +3069,16 @@ static int mtk_probe(struct platform_dev
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}
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}
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+ if (of_dma_is_coherent(pdev->dev.of_node)) {
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+ struct regmap *cci;
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+
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+ cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
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+ "mediatek,cci-control");
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+ /* enable CPU/bus coherency */
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+ if (!IS_ERR(cci))
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+ regmap_write(cci, 0, 3);
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+ }
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+
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
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eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii),
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GFP_KERNEL);
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@@ -437,6 +437,12 @@
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#define RSTCTRL_FE BIT(6)
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#define RSTCTRL_PPE BIT(31)
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+/* ethernet dma channel agent map */
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+#define ETHSYS_DMA_AG_MAP 0x408
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+#define ETHSYS_DMA_AG_MAP_PDMA BIT(0)
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+#define ETHSYS_DMA_AG_MAP_QDMA BIT(1)
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+#define ETHSYS_DMA_AG_MAP_PPE BIT(2)
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+
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/* SGMII subsystem config registers */
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/* Register to auto-negotiation restart */
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#define SGMSYS_PCS_CONTROL_1 0x0
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