95170b4350
this patch copies the following files from 5.4 to 5.10: - config-5.4 -> config-5.10 - files-5.4/ -> files-5.10/ - patches-5.4/ -> patches-5.10/ Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> [rebase on change in files-5.4] Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
429 lines
12 KiB
C
429 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _RTL838X_ETH_H
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#define _RTL838X_ETH_H
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/*
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* Register definition
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*/
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/* Per port MAC control */
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#define RTL838X_MAC_PORT_CTRL (0xd560)
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#define RTL839X_MAC_PORT_CTRL (0x8004)
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#define RTL930X_MAC_L2_PORT_CTRL (0x3268)
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#define RTL930X_MAC_PORT_CTRL (0x3260)
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#define RTL931X_MAC_L2_PORT_CTRL (0x6000)
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#define RTL931X_MAC_PORT_CTRL (0x6004)
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/* DMA interrupt control and status registers */
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#define RTL838X_DMA_IF_CTRL (0x9f58)
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#define RTL838X_DMA_IF_INTR_STS (0x9f54)
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#define RTL838X_DMA_IF_INTR_MSK (0x9f50)
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#define RTL839X_DMA_IF_CTRL (0x786c)
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#define RTL839X_DMA_IF_INTR_STS (0x7868)
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#define RTL839X_DMA_IF_INTR_MSK (0x7864)
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#define RTL930X_DMA_IF_CTRL (0xe028)
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#define RTL930X_DMA_IF_INTR_RX_RUNOUT_STS (0xe01C)
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#define RTL930X_DMA_IF_INTR_RX_DONE_STS (0xe020)
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#define RTL930X_DMA_IF_INTR_TX_DONE_STS (0xe024)
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#define RTL930X_DMA_IF_INTR_RX_RUNOUT_MSK (0xe010)
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#define RTL930X_DMA_IF_INTR_RX_DONE_MSK (0xe014)
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#define RTL930X_DMA_IF_INTR_TX_DONE_MSK (0xe018)
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#define RTL930X_L2_NTFY_IF_INTR_MSK (0xe04C)
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#define RTL930X_L2_NTFY_IF_INTR_STS (0xe050)
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/* TODO: RTL931X_DMA_IF_CTRL has different bits meanings */
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#define RTL931X_DMA_IF_CTRL (0x0928)
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#define RTL931X_DMA_IF_INTR_RX_RUNOUT_STS (0x091c)
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#define RTL931X_DMA_IF_INTR_RX_DONE_STS (0x0920)
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#define RTL931X_DMA_IF_INTR_TX_DONE_STS (0x0924)
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#define RTL931X_DMA_IF_INTR_RX_RUNOUT_MSK (0x0910)
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#define RTL931X_DMA_IF_INTR_RX_DONE_MSK (0x0914)
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#define RTL931X_DMA_IF_INTR_TX_DONE_MSK (0x0918)
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#define RTL931X_L2_NTFY_IF_INTR_MSK (0x09E4)
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#define RTL931X_L2_NTFY_IF_INTR_STS (0x09E8)
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#define RTL838X_MAC_FORCE_MODE_CTRL (0xa104)
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#define RTL839X_MAC_FORCE_MODE_CTRL (0x02bc)
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#define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C)
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#define RTL931X_MAC_FORCE_MODE_CTRL (0x0ddc)
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/* MAC address settings */
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#define RTL838X_MAC (0xa9ec)
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#define RTL839X_MAC (0x02b4)
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#define RTL838X_MAC_ALE (0x6b04)
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#define RTL838X_MAC2 (0xa320)
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#define RTL930X_MAC_L2_ADDR_CTRL (0xC714)
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#define RTL931X_MAC_L2_ADDR_CTRL (0x135c)
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/* Ringbuffer setup */
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#define RTL838X_DMA_RX_BASE (0x9f00)
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#define RTL839X_DMA_RX_BASE (0x780c)
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#define RTL930X_DMA_RX_BASE (0xdf00)
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#define RTL931X_DMA_RX_BASE (0x0800)
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#define RTL838X_DMA_TX_BASE (0x9f40)
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#define RTL839X_DMA_TX_BASE (0x784c)
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#define RTL930X_DMA_TX_BASE (0xe000)
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#define RTL931X_DMA_TX_BASE (0x0900)
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#define RTL838X_DMA_IF_RX_RING_SIZE (0xB7E4)
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#define RTL839X_DMA_IF_RX_RING_SIZE (0x6038)
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#define RTL930X_DMA_IF_RX_RING_SIZE (0x7C60)
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#define RTL931X_DMA_IF_RX_RING_SIZE (0x2080)
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#define RTL838X_DMA_IF_RX_RING_CNTR (0xB7E8)
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#define RTL839X_DMA_IF_RX_RING_CNTR (0x603c)
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#define RTL930X_DMA_IF_RX_RING_CNTR (0x7C8C)
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#define RTL931X_DMA_IF_RX_RING_CNTR (0x20AC)
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#define RTL838X_DMA_IF_RX_CUR (0x9F20)
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#define RTL839X_DMA_IF_RX_CUR (0x782c)
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#define RTL930X_DMA_IF_RX_CUR (0xdf80)
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#define RTL931X_DMA_IF_RX_CUR (0x0880)
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#define RTL838X_DMA_IF_TX_CUR_DESC_ADDR_CTRL (0x9F48)
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#define RTL930X_DMA_IF_TX_CUR_DESC_ADDR_CTRL (0xE008)
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#define RTL838X_DMY_REG31 (0x3b28)
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#define RTL838X_SDS_MODE_SEL (0x0028)
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#define RTL838X_SDS_CFG_REG (0x0034)
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#define RTL838X_INT_MODE_CTRL (0x005c)
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#define RTL838X_CHIP_INFO (0x00d8)
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#define RTL838X_SDS4_REG28 (0xef80)
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#define RTL838X_SDS4_DUMMY0 (0xef8c)
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#define RTL838X_SDS5_EXT_REG6 (0xf18c)
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/* L2 features */
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#define RTL839X_TBL_ACCESS_L2_CTRL (0x1180)
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#define RTL839X_TBL_ACCESS_L2_DATA(idx) (0x1184 + ((idx) << 2))
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#define RTL838X_TBL_ACCESS_CTRL_0 (0x6914)
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#define RTL838X_TBL_ACCESS_DATA_0(idx) (0x6918 + ((idx) << 2))
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/* MAC-side link state handling */
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#define RTL838X_MAC_LINK_STS (0xa188)
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#define RTL839X_MAC_LINK_STS (0x0390)
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#define RTL930X_MAC_LINK_STS (0xCB10)
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#define RTL931X_MAC_LINK_STS (0x0ec0)
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#define RTL838X_MAC_LINK_SPD_STS (0xa190)
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#define RTL839X_MAC_LINK_SPD_STS (0x03a0)
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#define RTL930X_MAC_LINK_SPD_STS (0xCB18)
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#define RTL931X_MAC_LINK_SPD_STS (0x0ed0)
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#define RTL838X_MAC_LINK_DUP_STS (0xa19c)
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#define RTL839X_MAC_LINK_DUP_STS (0x03b0)
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#define RTL930X_MAC_LINK_DUP_STS (0xCB28)
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#define RTL931X_MAC_LINK_DUP_STS (0x0ef0)
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// TODO: RTL8390_MAC_LINK_MEDIA_STS_ADDR ???
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#define RTL838X_MAC_TX_PAUSE_STS (0xa1a0)
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#define RTL839X_MAC_TX_PAUSE_STS (0x03b8)
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#define RTL930X_MAC_TX_PAUSE_STS (0xCB2C)
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#define RTL931X_MAC_TX_PAUSE_STS (0x0ef8)
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#define RTL838X_MAC_RX_PAUSE_STS (0xa1a4)
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#define RTL839X_MAC_RX_PAUSE_STS (0xCB30)
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#define RTL930X_MAC_RX_PAUSE_STS (0xC2F8)
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#define RTL931X_MAC_RX_PAUSE_STS (0x0f00)
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#define RTL838X_EEE_TX_TIMER_GIGA_CTRL (0xaa04)
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#define RTL838X_EEE_TX_TIMER_GELITE_CTRL (0xaa08)
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#define RTL930X_L2_UNKN_UC_FLD_PMSK (0x9064)
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#define RTL839X_MAC_GLB_CTRL (0x02a8)
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#define RTL839X_SCHED_LB_TICK_TKN_CTRL (0x60f8)
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#define RTL838X_L2_TBL_FLUSH_CTRL (0x3370)
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#define RTL839X_L2_TBL_FLUSH_CTRL (0x3ba0)
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#define RTL930X_L2_TBL_FLUSH_CTRL (0x9404)
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#define RTL931X_L2_TBL_FLUSH_CTRL (0xCD9C)
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#define RTL930X_L2_PORT_SABLK_CTRL (0x905c)
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#define RTL930X_L2_PORT_DABLK_CTRL (0x9060)
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/* MAC link state bits */
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#define FORCE_EN (1 << 0)
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#define FORCE_LINK_EN (1 << 1)
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#define NWAY_EN (1 << 2)
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#define DUPLX_MODE (1 << 3)
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#define TX_PAUSE_EN (1 << 6)
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#define RX_PAUSE_EN (1 << 7)
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/* L2 Notification DMA interface */
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#define RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL (0x785C)
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#define RTL839X_L2_NOTIFICATION_CTRL (0x7808)
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#define RTL931X_L2_NTFY_RING_BASE_ADDR (0x09DC)
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#define RTL931X_L2_NTFY_RING_CUR_ADDR (0x09E0)
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#define RTL839X_L2_NOTIFICATION_CTRL (0x7808)
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#define RTL931X_L2_NTFY_CTRL (0xCDC8)
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#define RTL838X_L2_CTRL_0 (0x3200)
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#define RTL839X_L2_CTRL_0 (0x3800)
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#define RTL930X_L2_CTRL (0x8FD8)
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#define RTL931X_L2_CTRL (0xC800)
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/* TRAPPING to CPU-PORT */
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#define RTL838X_SPCL_TRAP_IGMP_CTRL (0x6984)
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#define RTL838X_RMA_CTRL_0 (0x4300)
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#define RTL838X_RMA_CTRL_1 (0x4304)
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#define RTL839X_RMA_CTRL_0 (0x1200)
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#define RTL839X_SPCL_TRAP_IGMP_CTRL (0x1058)
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#define RTL839X_RMA_CTRL_1 (0x1204)
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#define RTL839X_RMA_CTRL_2 (0x1208)
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#define RTL839X_RMA_CTRL_3 (0x120C)
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#define RTL930X_VLAN_APP_PKT_CTRL (0xA23C)
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#define RTL930X_RMA_CTRL_0 (0x9E60)
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#define RTL930X_RMA_CTRL_1 (0x9E64)
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#define RTL930X_RMA_CTRL_2 (0x9E68)
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#define RTL931X_RMA_CTRL_0 (0x8800)
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#define RTL931X_RMA_CTRL_1 (0x8804)
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#define RTL931X_RMA_CTRL_2 (0x8808)
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/* Advanced SMI control for clause 45 PHYs */
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#define RTL930X_SMI_MAC_TYPE_CTRL (0xCA04)
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#define RTL930X_SMI_PORT24_27_ADDR_CTRL (0xCB90)
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#define RTL930X_SMI_PORT0_15_POLLING_SEL (0xCA08)
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#define RTL930X_SMI_PORT16_27_POLLING_SEL (0xCA0C)
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/* Registers of the internal Serdes of the 8390 */
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#define RTL839X_SDS12_13_XSG0 (0xB800)
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/* Registers of the internal Serdes of the 8380 */
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#define RTL838X_SDS4_FIB_REG0 (0xF800)
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inline int rtl838x_mac_port_ctrl(int p)
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{
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return RTL838X_MAC_PORT_CTRL + (p << 7);
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}
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inline int rtl839x_mac_port_ctrl(int p)
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{
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return RTL839X_MAC_PORT_CTRL + (p << 7);
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}
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/* On the RTL931XX, the functionality of the MAC port control register is split up
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* into RTL931X_MAC_L2_PORT_CTRL and RTL931X_MAC_PORT_CTRL the functionality used
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* by the Ethernet driver is in the same bits now in RTL931X_MAC_L2_PORT_CTRL
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*/
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inline int rtl930x_mac_port_ctrl(int p)
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{
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return RTL930X_MAC_L2_PORT_CTRL + (p << 6);
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}
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inline int rtl931x_mac_port_ctrl(int p)
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{
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return RTL931X_MAC_L2_PORT_CTRL + (p << 7);
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}
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inline int rtl838x_dma_if_rx_ring_size(int i)
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{
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return RTL838X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2);
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}
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inline int rtl839x_dma_if_rx_ring_size(int i)
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{
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return RTL839X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2);
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}
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inline int rtl930x_dma_if_rx_ring_size(int i)
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{
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return RTL930X_DMA_IF_RX_RING_SIZE + ((i / 3) << 2);
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}
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inline int rtl931x_dma_if_rx_ring_size(int i)
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{
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return RTL931X_DMA_IF_RX_RING_SIZE + ((i / 3) << 2);
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}
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inline int rtl838x_dma_if_rx_ring_cntr(int i)
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{
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return RTL838X_DMA_IF_RX_RING_CNTR + ((i >> 3) << 2);
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}
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inline int rtl839x_dma_if_rx_ring_cntr(int i)
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{
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return RTL839X_DMA_IF_RX_RING_CNTR + ((i >> 3) << 2);
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}
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inline int rtl930x_dma_if_rx_ring_cntr(int i)
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{
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return RTL930X_DMA_IF_RX_RING_CNTR + ((i / 3) << 2);
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}
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inline int rtl931x_dma_if_rx_ring_cntr(int i)
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{
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return RTL931X_DMA_IF_RX_RING_CNTR + ((i / 3) << 2);
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}
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inline u32 rtl838x_get_mac_link_sts(int port)
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{
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return (sw_r32(RTL838X_MAC_LINK_STS) & BIT(port));
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}
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inline u32 rtl839x_get_mac_link_sts(int p)
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{
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return (sw_r32(RTL839X_MAC_LINK_STS + ((p >> 5) << 2)) & BIT(p % 32));
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}
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inline u32 rtl930x_get_mac_link_sts(int port)
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{
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return (sw_r32(RTL930X_MAC_LINK_STS) & BIT(port));
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}
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inline u32 rtl931x_get_mac_link_sts(int p)
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{
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return (sw_r32(RTL931X_MAC_LINK_STS + ((p >> 5) << 2)) & BIT(p % 32));
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}
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inline u32 rtl838x_get_mac_link_dup_sts(int port)
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{
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return (sw_r32(RTL838X_MAC_LINK_DUP_STS) & BIT(port));
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}
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inline u32 rtl839x_get_mac_link_dup_sts(int p)
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{
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return (sw_r32(RTL839X_MAC_LINK_DUP_STS + ((p >> 5) << 2)) & BIT(p % 32));
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}
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inline u32 rtl930x_get_mac_link_dup_sts(int port)
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{
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return (sw_r32(RTL930X_MAC_LINK_DUP_STS) & BIT(port));
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}
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inline u32 rtl931x_get_mac_link_dup_sts(int p)
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{
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return (sw_r32(RTL931X_MAC_LINK_DUP_STS + ((p >> 5) << 2)) & BIT(p % 32));
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}
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inline u32 rtl838x_get_mac_link_spd_sts(int port)
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{
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int r = RTL838X_MAC_LINK_SPD_STS + ((port >> 4) << 2);
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u32 speed = sw_r32(r);
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speed >>= (port % 16) << 1;
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return (speed & 0x3);
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}
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inline u32 rtl839x_get_mac_link_spd_sts(int port)
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{
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int r = RTL839X_MAC_LINK_SPD_STS + ((port >> 4) << 2);
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u32 speed = sw_r32(r);
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speed >>= (port % 16) << 1;
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return (speed & 0x3);
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}
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inline u32 rtl930x_get_mac_link_spd_sts(int port)
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{
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int r = RTL930X_MAC_LINK_SPD_STS + ((port / 10) << 2);
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u32 speed = sw_r32(r);
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speed >>= (port % 10) * 3;
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return (speed & 0x7);
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}
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inline u32 rtl931x_get_mac_link_spd_sts(int port)
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{
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int r = RTL931X_MAC_LINK_SPD_STS + ((port >> 3) << 2);
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u32 speed = sw_r32(r);
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speed >>= (port % 8) << 2;
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return (speed & 0xf);
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}
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inline u32 rtl838x_get_mac_rx_pause_sts(int port)
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{
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return (sw_r32(RTL838X_MAC_RX_PAUSE_STS) & (1 << port));
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}
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inline u32 rtl839x_get_mac_rx_pause_sts(int p)
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{
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return (sw_r32(RTL839X_MAC_RX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32));
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}
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inline u32 rtl930x_get_mac_rx_pause_sts(int port)
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{
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return (sw_r32(RTL930X_MAC_RX_PAUSE_STS) & (1 << port));
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}
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inline u32 rtl931x_get_mac_rx_pause_sts(int p)
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{
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return (sw_r32(RTL931X_MAC_RX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32));
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}
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inline u32 rtl838x_get_mac_tx_pause_sts(int port)
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{
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return (sw_r32(RTL838X_MAC_TX_PAUSE_STS) & (1 << port));
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}
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inline u32 rtl839x_get_mac_tx_pause_sts(int p)
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{
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return (sw_r32(RTL839X_MAC_TX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32));
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}
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inline u32 rtl930x_get_mac_tx_pause_sts(int port)
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{
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return (sw_r32(RTL930X_MAC_TX_PAUSE_STS) & (1 << port));
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}
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inline u32 rtl931x_get_mac_tx_pause_sts(int p)
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{
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return (sw_r32(RTL931X_MAC_TX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32));
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}
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struct p_hdr;
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struct dsa_tag;
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struct rtl838x_reg {
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irqreturn_t (*net_irq)(int irq, void *dev_id);
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int (*mac_port_ctrl)(int port);
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int dma_if_intr_sts;
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int dma_if_intr_msk;
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int dma_if_intr_rx_runout_sts;
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int dma_if_intr_rx_done_sts;
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int dma_if_intr_tx_done_sts;
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int dma_if_intr_rx_runout_msk;
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int dma_if_intr_rx_done_msk;
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int dma_if_intr_tx_done_msk;
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int l2_ntfy_if_intr_sts;
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int l2_ntfy_if_intr_msk;
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int dma_if_ctrl;
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int mac_force_mode_ctrl;
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int dma_rx_base;
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int dma_tx_base;
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int (*dma_if_rx_ring_size)(int ring);
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int (*dma_if_rx_ring_cntr)(int ring);
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int dma_if_rx_cur;
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int rst_glb_ctrl;
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u32 (*get_mac_link_sts)(int port);
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u32 (*get_mac_link_dup_sts)(int port);
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u32 (*get_mac_link_spd_sts)(int port);
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u32 (*get_mac_rx_pause_sts)(int port);
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u32 (*get_mac_tx_pause_sts)(int port);
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int mac;
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int l2_tbl_flush_ctrl;
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void (*update_cntr)(int r, int work_done);
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void (*create_tx_header)(struct p_hdr *h, int dest_port, int prio);
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bool (*decode_tag)(struct p_hdr *h, struct dsa_tag *tag);
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};
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int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val);
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int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
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int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val);
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int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
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int rtl930x_write_phy(u32 port, u32 page, u32 reg, u32 val);
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int rtl930x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
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int rtl931x_write_phy(u32 port, u32 page, u32 reg, u32 val);
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int rtl931x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
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void rtl9300_sds_power(int sds_num, int val);
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#endif /* _RTL838X_ETH_H */
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