df8e6be59a
This adds support for the RTL838x Architecture. SoCs of this type are used in managed and un-managed Switches and Routers with 8-28 ports. Drivers are provided for SoC initialization, GPIOs, Flash, Ethernet including a DSA switch driver and internal and external PHYs used with these switches. Supported SoCs: RTL8380M RTL8381M RTL8382M The kernel will also boot on the following RTL839x SoCs, however driver support apart from spi-nor is missing: RTL8390 RTL8391 RTL8393 The following PHYs are supported: RTL8214FC (Quad QSGMII multiplexing GMAC and SFP port) RTL8218B internal: internal PHY of the RTL838x chips RTL8318b external (QSGMII 8-port GMAC phy) RTL8382M SerDes for 2 SFP ports Initialization sequences for the PHYs are provided in the form of firmware files. Flash driver supports 3 / 4 byte access DSA switch driver supports VLANs, port isolation, STP and port mirroring. The ALLNET ALL-SG8208M is supported as Proof of Concept: RTL8382M SoC 1 MIPS 4KEc core @ 500MHz 8 Internal PHYs (RTL8218B) 128MB DRAM (Nanya NT5TU128MB) 16MB NOR Flash (MXIC 25L128) 8 GBEthernet ports with one green status LED each (SoC controlled) 1 Power LED (not configurable) 1 SYS LED (configurable) 1 On-Off switch (not configurable) 1 Reset button at the right behind right air-vent (not configurable) 1 Reset button on front panel (configurable) 12V 1A barrel connector 1 serial header with populated standard pin connector and with markings GND TX RX Vcc(3.3V), connection properties: 115200 8N1 To install, upload the sysupgrade image to the OEM webpage. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
261 lines
7.1 KiB
C
261 lines
7.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _RTL838X_ETH_H
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#define _RTL838X_ETH_H
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/*
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* Register definition
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*/
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#define RTL838X_CPU_PORT 28
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#define RTL839X_CPU_PORT 52
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#define RTL838X_MAC_PORT_CTRL (0xd560)
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#define RTL839X_MAC_PORT_CTRL (0x8004)
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#define RTL838X_DMA_IF_INTR_STS (0x9f54)
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#define RTL839X_DMA_IF_INTR_STS (0x7868)
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#define RTL838X_DMA_IF_INTR_MSK (0x9f50)
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#define RTL839X_DMA_IF_INTR_MSK (0x7864)
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#define RTL838X_DMA_IF_CTRL (0x9f58)
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#define RTL839X_DMA_IF_CTRL (0x786c)
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#define RTL838X_RST_GLB_CTRL_0 (0x003c)
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#define RTL838X_MAC_FORCE_MODE_CTRL (0xa104)
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#define RTL839X_MAC_FORCE_MODE_CTRL (0x02bc)
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/* MAC address settings */
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#define RTL838X_MAC (0xa9ec)
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#define RTL839X_MAC (0x02b4)
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#define RTL838X_MAC_ALE (0x6b04)
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#define RTL838X_MAC2 (0xa320)
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#define RTL838X_DMA_RX_BASE (0x9f00)
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#define RTL839X_DMA_RX_BASE (0x780c)
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#define RTL838X_DMA_TX_BASE (0x9f40)
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#define RTL839X_DMA_TX_BASE (0x784c)
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#define RTL838X_DMA_IF_RX_RING_SIZE (0xB7E4)
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#define RTL839X_DMA_IF_RX_RING_SIZE (0x6038)
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#define RTL838X_DMA_IF_RX_RING_CNTR (0xB7E8)
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#define RTL839X_DMA_IF_RX_RING_CNTR (0x603c)
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#define RTL838X_DMA_IF_RX_CUR (0x9F20)
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#define RTL839X_DMA_IF_RX_CUR (0x782c)
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#define RTL838X_DMY_REG31 (0x3b28)
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#define RTL838X_SDS_MODE_SEL (0x0028)
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#define RTL838X_SDS_CFG_REG (0x0034)
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#define RTL838X_INT_MODE_CTRL (0x005c)
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#define RTL838X_CHIP_INFO (0x00d8)
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#define RTL838X_SDS4_REG28 (0xef80)
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#define RTL838X_SDS4_DUMMY0 (0xef8c)
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#define RTL838X_SDS5_EXT_REG6 (0xf18c)
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#define RTL838X_PORT_ISO_CTRL(port) (0x4100 + ((port) << 2))
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#define RTL838X_STAT_PORT_STD_MIB(port) (0x1200 + (((port) << 8)))
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#define RTL838X_STAT_RST (0x3100)
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#define RTL838X_STAT_CTRL (0x3108)
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/* Registers of the internal Serdes of the 8380 */
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#define MAPLE_SDS4_REG0r RTL838X_SDS4_REG28
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#define MAPLE_SDS5_REG0r (RTL838X_SDS4_REG28 + 0x100)
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#define MAPLE_SDS4_REG3r RTL838X_SDS4_DUMMY0
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#define MAPLE_SDS5_REG3r (RTL838X_SDS4_REG28 + 0x100)
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#define MAPLE_SDS4_FIB_REG0r (RTL838X_SDS4_REG28 + 0x880)
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#define MAPLE_SDS5_FIB_REG0r (RTL838X_SDS4_REG28 + 0x980)
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/* VLAN registers */
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#define RTL838X_VLAN_PROFILE(idx) (0x3A88 + ((idx) << 2))
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#define RTL838X_VLAN_PORT_EGR_FLTR (0x3A84)
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#define RTL838X_VLAN_PORT_PB_VLAN(port) (0x3C00 + ((port) << 2))
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#define RTL838X_VLAN_PORT_IGR_FLTR_0 (0x3A7C)
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#define RTL838X_VLAN_PORT_IGR_FLTR_1 (0x3A7C + 4)
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#define RTL838X_TBL_ACCESS_CTRL_0 (0x6914)
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#define RTL838X_TBL_ACCESS_DATA_0(idx) (0x6918 + ((idx) << 2))
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#define RTL838X_TBL_ACCESS_CTRL_1 (0xA4C8)
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#define RTL838X_TBL_ACCESS_DATA_1(idx) (0xA4CC + ((idx) << 2))
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#define RTL839X_TBL_ACCESS_L2_CTRL (0x1180)
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#define RTL839X_TBL_ACCESS_L2_DATA(idx) (0x1184 + ((idx) << 2))
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/* MAC handling */
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#define RTL838X_MAC_LINK_STS (0xa188)
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#define RTL839X_MAC_LINK_STS (0x0390)
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#define RTL838X_MAC_LINK_SPD_STS (0xa190)
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#define RTL839X_MAC_LINK_SPD_STS (0x03a0)
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#define RTL838X_MAC_LINK_DUP_STS (0xa19c)
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#define RTL839X_MAC_LINK_DUP_STS (0x03b0)
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// TODO: RTL8390_MAC_LINK_MEDIA_STS_ADDR ???
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#define RTL838X_MAC_TX_PAUSE_STS (0xa1a0)
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#define RTL839X_MAC_TX_PAUSE_STS (0x03b8)
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#define RTL838X_MAC_RX_PAUSE_STS (0xa1a4)
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#define RTL839X_MAC_RX_PAUSE_STS (0x03c0)
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#define RTL838X_EEE_TX_TIMER_GIGA_CTRL (0xaa04)
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#define RTL838X_EEE_TX_TIMER_GELITE_CTRL (0xaa08)
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#define RTL839X_MAC_GLB_CTRL (0x02a8)
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#define RTL839X_SCHED_LB_TICK_TKN_CTRL (0x60f8)
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#define RTL838X_L2_TBL_FLUSH_CTRL (0x3370)
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#define RTL839X_L2_TBL_FLUSH_CTRL (0x3ba0)
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/* MAC link state bits */
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#define FORCE_EN (1 << 0)
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#define FORCE_LINK_EN (1 << 1)
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#define NWAY_EN (1 << 2)
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#define DUPLX_MODE (1 << 3)
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#define TX_PAUSE_EN (1 << 6)
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#define RX_PAUSE_EN (1 << 7)
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inline int rtl838x_mac_port_ctrl(int p)
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{
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return RTL838X_MAC_PORT_CTRL + (p << 7);
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}
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inline int rtl839x_mac_port_ctrl(int p)
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{
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return RTL839X_MAC_PORT_CTRL + (p << 7);
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}
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static inline int rtl838x_mac_force_mode_ctrl(int p)
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{
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return RTL838X_MAC_FORCE_MODE_CTRL + (p << 2);
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}
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static inline int rtl839x_mac_force_mode_ctrl(int p)
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{
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return RTL839X_MAC_FORCE_MODE_CTRL + (p << 2);
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}
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inline int rtl838x_dma_rx_base(int i)
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{
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return RTL838X_DMA_RX_BASE + (i << 2);
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}
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inline int rtl839x_dma_rx_base(int i)
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{
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return RTL839X_DMA_RX_BASE + (i << 2);
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}
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inline int rtl838x_dma_tx_base(int i)
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{
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return RTL838X_DMA_TX_BASE + (i << 2);
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}
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inline int rtl839x_dma_tx_base(int i)
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{
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return RTL839X_DMA_TX_BASE + (i << 2);
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}
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inline int rtl838x_dma_if_rx_ring_size(int i)
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{
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return RTL838X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2);
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}
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inline int rtl839x_dma_if_rx_ring_size(int i)
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{
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return RTL839X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2);
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}
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inline int rtl838x_dma_if_rx_ring_cntr(int i)
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{
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return RTL838X_DMA_IF_RX_RING_CNTR + ((i >> 3) << 2);
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}
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inline int rtl839x_dma_if_rx_ring_cntr(int i)
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{
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return RTL839X_DMA_IF_RX_RING_CNTR + ((i >> 3) << 2);
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}
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inline int rtl838x_dma_if_rx_cur(int i)
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{
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return RTL838X_DMA_IF_RX_CUR + (i << 2);
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}
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inline int rtl839x_dma_if_rx_cur(int i)
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{
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return RTL839X_DMA_IF_RX_CUR + (i << 2);
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}
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inline u32 rtl838x_get_mac_link_sts(int port)
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{
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return (sw_r32(RTL838X_MAC_LINK_STS) & (1 << port));
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}
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inline u32 rtl839x_get_mac_link_sts(int p)
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{
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return (sw_r32(RTL839X_MAC_LINK_STS + ((p >> 5) << 2)) & (1 << p));
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}
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inline u32 rtl838x_get_mac_link_dup_sts(int port)
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{
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return (sw_r32(RTL838X_MAC_LINK_DUP_STS) & (1 << port));
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}
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inline u32 rtl839x_get_mac_link_dup_sts(int p)
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{
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return (sw_r32(RTL839X_MAC_LINK_DUP_STS + ((p >> 5) << 2)) & (1 << p));
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}
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inline u32 rtl838x_get_mac_link_spd_sts(int port)
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{
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int r = RTL838X_MAC_LINK_SPD_STS + ((port >> 4) << 2);
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u32 speed = sw_r32(r);
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speed >>= (port % 16) << 1;
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return (speed & 0x3);
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}
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inline u32 rtl839x_get_mac_link_spd_sts(int port)
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{
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int r = RTL839X_MAC_LINK_SPD_STS + ((port >> 4) << 2);
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u32 speed = sw_r32(r);
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speed >>= (port % 16) << 1;
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return (speed & 0x3);
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}
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inline u32 rtl838x_get_mac_rx_pause_sts(int port)
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{
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return (sw_r32(RTL838X_MAC_RX_PAUSE_STS) & (1 << port));
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}
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inline u32 rtl839x_get_mac_rx_pause_sts(int p)
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{
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return (sw_r32(RTL839X_MAC_RX_PAUSE_STS + ((p >> 5) << 2)) & (1 << p));
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}
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inline u32 rtl838x_get_mac_tx_pause_sts(int port)
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{
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return (sw_r32(RTL838X_MAC_TX_PAUSE_STS) & (1 << port));
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}
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inline u32 rtl839x_get_mac_tx_pause_sts(int p)
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{
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return (sw_r32(RTL839X_MAC_TX_PAUSE_STS + ((p >> 5) << 2)) & (1 << p));
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}
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struct rtl838x_reg {
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int (*mac_port_ctrl)(int port);
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int dma_if_intr_sts;
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int dma_if_intr_msk;
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int dma_if_ctrl;
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int (*mac_force_mode_ctrl)(int port);
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int (*dma_rx_base)(int ring);
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int (*dma_tx_base)(int ring);
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int (*dma_if_rx_ring_size)(int ring);
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int (*dma_if_rx_ring_cntr)(int ring);
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int (*dma_if_rx_cur)(int ring);
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int rst_glb_ctrl;
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u32 (*get_mac_link_sts)(int port);
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u32 (*get_mac_link_dup_sts)(int port);
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u32 (*get_mac_link_spd_sts)(int port);
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u32 (*get_mac_rx_pause_sts)(int port);
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u32 (*get_mac_tx_pause_sts)(int port);
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int mac;
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int l2_tbl_flush_ctrl;
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};
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int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val);
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int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
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int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val);
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int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
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extern int rtl8380_sds_power(int mac, int val);
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#endif /* _RTL838X_ETH_H */
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