c1c1112006
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These instructions are for 64-bit load/store. On ARMv5TE, the CPU requires addresses to be aligned to 64-bit. When misaligned, behavior is undefined (effectively either loads the same word twice on LDRD, or corrupts surrounding memory on STRD). On ARMv6 and newer, unaligned access is safe. Removing these instructions for ARMv5TE is necessary, because GCC ignores alignment information in pointers and does unsafe optimizations that have shown up as bugs in various places. This patch was originally added more than 11 years ago in commitb050f87d13, but got lost 6 years ago, when gcc 9.1 was added in88c07c6552. This primarily affects the kirkwood and ixp4xx targets Signed-off-by: Felix Fietkau <nbd@nbd.name>
11 lines
426 B
Diff
11 lines
426 B
Diff
--- a/gcc/config/arm/arm.h
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+++ b/gcc/config/arm/arm.h
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@@ -165,7 +165,7 @@ emission of floating point pcs attribute
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/* Thumb-1 only. */
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#define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm)
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-#define TARGET_LDRD (arm_arch5te && ARM_DOUBLEWORD_ALIGN \
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+#define TARGET_LDRD (arm_arch6 && ARM_DOUBLEWORD_ALIGN \
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&& !TARGET_THUMB1)
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#define TARGET_CRC32 (arm_arch_crc)
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