c057db94f8
Siflower SF21A6826/SF21H8898 are a family of RISC-V SoCs with: * Quad-core T-Head C908 (1.125G for SF21A6826, 1.25G for SF21H8898) * DDR3/DDR4 memory controller * 1 QSGMII 4x1G * 1 SGMII/2500Base-X 2.5G * 1 additional RGMII on SF21H8898 * Network offloading engine for L2 switching and L3 NAT * 2 PCIE Gen2 lanes, operating in either one PCIE Gen2x2 or two PCIE Gen2x1 mode * 1 USB2.0 Link: https://github.com/openwrt/openwrt/pull/17115 Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
29 lines
680 B
C
29 lines
680 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _SF21_RESETS_H
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#define _SF21_RESETS_H
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#define SF21_RESET_GIC 0
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#define SF21_RESET_AXI 1
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#define SF21_RESET_AHB 2
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#define SF21_RESET_APB 3
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#define SF21_RESET_IRAM 4
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#define SF21_RESET_NPU 5
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#define SF21_RESET_DDR_CTL 6
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#define SF21_RESET_DDR_PHY 7
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#define SF21_RESET_DDR_PWR_OK_IN 8
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#define SF21_RESET_DDR_CTL_APB 9
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#define SF21_RESET_DDR_PHY_APB 10
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#define SF21_RESET_USB 11
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#define SF21_RESET_PVT 12
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#define SF21_RESET_SERDES_CSR 13
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#define SF21_RESET_CRYPT_CSR 14
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#define SF21_RESET_CRYPT_APP 15
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#define SF21_RESET_NPU2DDR_ASYNCBRIDGE 16
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#define SF21_RESET_IROM 17
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#define SF21_RESET_MAX 17
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#endif
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