c057db94f8
Siflower SF21A6826/SF21H8898 are a family of RISC-V SoCs with: * Quad-core T-Head C908 (1.125G for SF21A6826, 1.25G for SF21H8898) * DDR3/DDR4 memory controller * 1 QSGMII 4x1G * 1 SGMII/2500Base-X 2.5G * 1 additional RGMII on SF21H8898 * Network offloading engine for L2 switching and L3 NAT * 2 PCIE Gen2 lanes, operating in either one PCIE Gen2x2 or two PCIE Gen2x1 mode * 1 USB2.0 Link: https://github.com/openwrt/openwrt/pull/17115 Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
43 lines
876 B
C
43 lines
876 B
C
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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#define CLK_CMNPLL_VCO 0
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#define CLK_CMNPLL_POSTDIV 1
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#define CLK_DDRPLL_POSTDIV 2
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#define CLK_PCIEPLL_VCO 3
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#define CLK_PCIEPLL_FOUT0 4
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#define CLK_PCIEPLL_FOUT1 5
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#define CLK_PCIEPLL_FOUT2 6
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#define CLK_ETH_REF_P CLK_PCIEPLL_FOUT2
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#define CLK_PCIEPLL_FOUT3 7
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#define CLK_CPU 8
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#define CLK_PIC 9
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#define CLK_AXI 10
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#define CLK_AHB 11
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#define CLK_APB 12
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#define CLK_UART 13
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#define CLK_IRAM 14
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#define CLK_NPU 15
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#define CLK_DDRPHY_REF 16
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#define CLK_DDR_BYPASS 17
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#define CLK_ETHTSU 18
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#define CLK_GMAC_BYP_REF 19
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#define CLK_USB 20
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#define CLK_USBPHY 21
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#define CLK_SERDES_CSR 22
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#define CLK_CRYPT_CSR 23
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#define CLK_CRYPT_APP 24
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#define CLK_IROM 25
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#define CLK_BOOT 26
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#define CLK_PVT 27
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#define CLK_PLL_TEST 28
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#define CLK_PCIE_REFN 29
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#define CLK_PCIE_REFP 30
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#define CLK_MAX 31
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