9a59eac049
Remove upstreamed patches and refresh remaining ones. Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> Link: https://github.com/openwrt/openwrt/pull/18683 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
105 lines
3.7 KiB
Diff
105 lines
3.7 KiB
Diff
From 2d81e1bb625238d40a686ed909ff3e1abab7556a Mon Sep 17 00:00:00 2001
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From: Dmitry Osipenko <dmitry.osipenko@collabora.com>
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Date: Mon, 17 Feb 2025 01:16:32 +0300
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Subject: [PATCH] irqchip/gic-v3: Add Rockchip 3568002 erratum workaround
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Rockchip RK3566/RK3568 GIC600 integration has DDR addressing
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limited to the first 32bit of physical address space. Rockchip
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assigned Erratum ID #3568002 for this issue. Add driver quirk for
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this Rockchip GIC Erratum.
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Note, that the 0x0201743b GIC600 ID is not Rockchip-specific and is
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common for many ARM GICv3 implementations. Hence, there is an extra
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of_machine_is_compatible() check.
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Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Acked-by: Marc Zyngier <maz@kernel.org>
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Link: https://lore.kernel.org/all/20250216221634.364158-2-dmitry.osipenko@collabora.com
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---
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Documentation/arch/arm64/silicon-errata.rst | 2 ++
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arch/arm64/Kconfig | 9 ++++++++
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drivers/irqchip/irq-gic-v3-its.c | 23 ++++++++++++++++++++-
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3 files changed, 33 insertions(+), 1 deletion(-)
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--- a/Documentation/arch/arm64/silicon-errata.rst
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+++ b/Documentation/arch/arm64/silicon-errata.rst
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@@ -283,6 +283,8 @@ stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
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| Rockchip | RK3588 | #3588001 | ROCKCHIP_ERRATUM_3588001 |
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+----------------+-----------------+-----------------+-----------------------------+
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+| Rockchip | RK3568 | #3568002 | ROCKCHIP_ERRATUM_3568002 |
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++----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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| Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 |
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+----------------+-----------------+-----------------+-----------------------------+
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--- a/arch/arm64/Kconfig
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+++ b/arch/arm64/Kconfig
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@@ -1295,6 +1295,15 @@ config NVIDIA_CARMEL_CNP_ERRATUM
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If unsure, say Y.
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+config ROCKCHIP_ERRATUM_3568002
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+ bool "Rockchip 3568002: GIC600 can not access physical addresses higher than 4GB"
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+ default y
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+ help
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+ The Rockchip RK3566 and RK3568 GIC600 SoC integrations have AXI
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+ addressing limited to the first 32bit of physical address space.
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+
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+ If unsure, say Y.
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+
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config ROCKCHIP_ERRATUM_3588001
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bool "Rockchip 3588001: GIC600 can not support shareability attributes"
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default y
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--- a/drivers/irqchip/irq-gic-v3-its.c
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+++ b/drivers/irqchip/irq-gic-v3-its.c
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@@ -205,13 +205,15 @@ static DEFINE_IDA(its_vpeid_ida);
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#define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
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#define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K)
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+static gfp_t gfp_flags_quirk;
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+
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static struct page *its_alloc_pages_node(int node, gfp_t gfp,
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unsigned int order)
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{
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struct page *page;
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int ret = 0;
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- page = alloc_pages_node(node, gfp, order);
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+ page = alloc_pages_node(node, gfp | gfp_flags_quirk, order);
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if (!page)
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return NULL;
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@@ -4888,6 +4890,17 @@ static bool __maybe_unused its_enable_qu
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return true;
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}
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+static bool __maybe_unused its_enable_rk3568002(void *data)
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+{
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+ if (!of_machine_is_compatible("rockchip,rk3566") &&
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+ !of_machine_is_compatible("rockchip,rk3568"))
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+ return false;
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+
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+ gfp_flags_quirk |= GFP_DMA32;
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+
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+ return true;
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+}
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+
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static const struct gic_quirk its_quirks[] = {
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#ifdef CONFIG_CAVIUM_ERRATUM_22375
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{
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@@ -4955,6 +4968,14 @@ static const struct gic_quirk its_quirks
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.property = "dma-noncoherent",
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.init = its_set_non_coherent,
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},
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+#ifdef CONFIG_ROCKCHIP_ERRATUM_3568002
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+ {
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+ .desc = "ITS: Rockchip erratum RK3568002",
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+ .iidr = 0x0201743b,
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+ .mask = 0xffffffff,
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+ .init = its_enable_rk3568002,
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+ },
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+#endif
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{
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}
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};
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