1308b4fb1c
Some DTS files have a qsgmii link mode for the CPU port. This does not harm but it is wrong. The CPU port of the realtek switch is always directly connected to the switch by some unknown wiring and should therefore be described as internal. Align the wrongly defined DTS files to the standard. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Link: https://github.com/openwrt/openwrt/pull/18691 Signed-off-by: Robert Marko <robimarko@gmail.com>
163 lines
3.4 KiB
Text
163 lines
3.4 KiB
Text
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "rtl839x.dtsi"
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#include "rtl83xx_d-link_dgs-1210_common.dtsi"
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#include "rtl83xx_d-link_dgs-1210_gpio.dtsi"
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#include "rtl83xx_d-link_dgs-1210_gpio_sfp.dtsi"
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/ {
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compatible = "d-link,dgs-1210-52", "realtek,rtl8393-soc";
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model = "D-Link DGS-1210-52";
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};
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ðernet0 {
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mdio: mdio-bus {
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compatible = "realtek,rtl838x-mdio";
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regmap = <ðernet0>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* External phy RTL8218B #1 */
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EXTERNAL_PHY(0)
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EXTERNAL_PHY(1)
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EXTERNAL_PHY(2)
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EXTERNAL_PHY(3)
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EXTERNAL_PHY(4)
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EXTERNAL_PHY(5)
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EXTERNAL_PHY(6)
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EXTERNAL_PHY(7)
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/* External phy RTL8218B #2 */
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EXTERNAL_PHY(8)
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EXTERNAL_PHY(9)
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EXTERNAL_PHY(10)
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EXTERNAL_PHY(11)
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EXTERNAL_PHY(12)
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EXTERNAL_PHY(13)
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EXTERNAL_PHY(14)
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EXTERNAL_PHY(15)
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/* External phy RTL8218B #3 */
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EXTERNAL_PHY(16)
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EXTERNAL_PHY(17)
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EXTERNAL_PHY(18)
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EXTERNAL_PHY(19)
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EXTERNAL_PHY(20)
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EXTERNAL_PHY(21)
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EXTERNAL_PHY(22)
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EXTERNAL_PHY(23)
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/* External phy RTL8218B #4 */
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EXTERNAL_PHY(24)
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EXTERNAL_PHY(25)
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EXTERNAL_PHY(26)
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EXTERNAL_PHY(27)
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EXTERNAL_PHY(28)
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EXTERNAL_PHY(29)
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EXTERNAL_PHY(30)
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EXTERNAL_PHY(31)
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/* External phy RTL8218B #5 */
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EXTERNAL_PHY(32)
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EXTERNAL_PHY(33)
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EXTERNAL_PHY(34)
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EXTERNAL_PHY(35)
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EXTERNAL_PHY(36)
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EXTERNAL_PHY(37)
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EXTERNAL_PHY(38)
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EXTERNAL_PHY(39)
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/* External phy RTL8218B #6 */
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EXTERNAL_PHY(40)
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EXTERNAL_PHY(41)
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EXTERNAL_PHY(42)
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EXTERNAL_PHY(43)
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EXTERNAL_PHY(44)
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EXTERNAL_PHY(45)
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EXTERNAL_PHY(46)
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EXTERNAL_PHY(47)
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/* External phy RTL8214FC */
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EXTERNAL_SFP_PHY_FULL(48, 0)
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EXTERNAL_SFP_PHY_FULL(49, 1)
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EXTERNAL_SFP_PHY_FULL(50, 2)
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EXTERNAL_SFP_PHY_FULL(51, 3)
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};
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};
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&switch0 {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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SWITCH_PORT(0, 1, qsgmii)
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SWITCH_PORT(1, 2, qsgmii)
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SWITCH_PORT(2, 3, qsgmii)
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SWITCH_PORT(3, 4, qsgmii)
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SWITCH_PORT(4, 5, qsgmii)
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SWITCH_PORT(5, 6, qsgmii)
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SWITCH_PORT(6, 7, qsgmii)
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SWITCH_PORT(7, 8, qsgmii)
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SWITCH_PORT(8, 9, qsgmii)
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SWITCH_PORT(9, 10, qsgmii)
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SWITCH_PORT(10, 11, qsgmii)
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SWITCH_PORT(11, 12, qsgmii)
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SWITCH_PORT(12, 13, qsgmii)
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SWITCH_PORT(13, 14, qsgmii)
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SWITCH_PORT(14, 15, qsgmii)
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SWITCH_PORT(15, 16, qsgmii)
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SWITCH_PORT(16, 17, qsgmii)
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SWITCH_PORT(17, 18, qsgmii)
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SWITCH_PORT(18, 19, qsgmii)
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SWITCH_PORT(19, 20, qsgmii)
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SWITCH_PORT(20, 21, qsgmii)
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SWITCH_PORT(21, 22, qsgmii)
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SWITCH_PORT(22, 23, qsgmii)
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SWITCH_PORT(23, 24, qsgmii)
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SWITCH_PORT(24, 25, qsgmii)
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SWITCH_PORT(25, 26, qsgmii)
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SWITCH_PORT(26, 27, qsgmii)
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SWITCH_PORT(27, 28, qsgmii)
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SWITCH_PORT(28, 29, qsgmii)
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SWITCH_PORT(29, 30, qsgmii)
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SWITCH_PORT(30, 31, qsgmii)
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SWITCH_PORT(31, 32, qsgmii)
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SWITCH_PORT(32, 33, qsgmii)
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SWITCH_PORT(33, 34, qsgmii)
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SWITCH_PORT(34, 35, qsgmii)
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SWITCH_PORT(35, 36, qsgmii)
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SWITCH_PORT(36, 37, qsgmii)
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SWITCH_PORT(37, 38, qsgmii)
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SWITCH_PORT(38, 39, qsgmii)
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SWITCH_PORT(39, 40, qsgmii)
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SWITCH_PORT(40, 41, qsgmii)
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SWITCH_PORT(41, 42, qsgmii)
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SWITCH_PORT(42, 43, qsgmii)
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SWITCH_PORT(43, 44, qsgmii)
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SWITCH_PORT(44, 45, qsgmii)
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SWITCH_PORT(45, 46, qsgmii)
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SWITCH_PORT(46, 47, qsgmii)
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SWITCH_PORT(47, 48, qsgmii)
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SWITCH_PORT(48, 49, qsgmii)
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SWITCH_PORT(49, 50, qsgmii)
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SWITCH_PORT(50, 51, qsgmii)
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SWITCH_PORT(51, 52, qsgmii)
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/* CPU-Port */
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port@52 {
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ethernet = <ðernet0>;
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reg = <52>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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