57aa05e8e5
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.12.37 Manually rebased patch: generic/hack-6.12/902-debloat_proc.patch[1] New Kconfig symbol: x86: enable MITIGATION_TSA[2] All other patches are automatically refreshed. [1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.12.37&id=ead91de35d9cd5c4f80ec51e6020f342079170af [2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.12.37&id=7a0395f6607a5d01e2b2a86355596b3f1224acbd Signed-off-by: Shiji Yang <yangshiji66@outlook.com> Link: https://github.com/openwrt/openwrt/pull/19317 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
81 lines
2.8 KiB
Diff
81 lines
2.8 KiB
Diff
From: Shiji Yang <yangshiji66@outlook.com>
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Date: Sat, 24 May 2025 15:53:26 +0800
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Subject: [PATCH 1/3] mmc: mtk-sd: add tuning parameters for legacy MIPS MT762x
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SoCs
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The MIPS MT762x SoCs require some specific tuning parameters at
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different clock frequencies. These legacy SoCs only support max
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48~50 MHz High-Speed SD mode. Therefore, the standard tuning step
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is not available. We have to hard code these tuning parameters
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to make them work properly.
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Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
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---
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drivers/mmc/host/mtk-sd.c | 26 +++++++++++++++++++++++++-
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1 file changed, 25 insertions(+), 1 deletion(-)
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--- a/drivers/mmc/host/mtk-sd.c
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+++ b/drivers/mmc/host/mtk-sd.c
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@@ -75,8 +75,13 @@
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#define MSDC_PATCH_BIT 0xb0
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#define MSDC_PATCH_BIT1 0xb4
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#define MSDC_PATCH_BIT2 0xb8
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+#define MSDC_PAD_CTRL0 0xe0
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+#define MSDC_PAD_CTRL1 0xe4
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+#define MSDC_PAD_CTRL2 0xe8
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#define MSDC_PAD_TUNE 0xec
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#define MSDC_PAD_TUNE0 0xf0
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+#define MSDC_DAT_RDDLY0 0xf0
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+#define MSDC_DAT_RDDLY1 0xf4
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#define PAD_DS_TUNE 0x188
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#define PAD_CMD_TUNE 0x18c
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#define EMMC51_CFG0 0x204
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@@ -408,6 +413,7 @@ struct mtk_mmc_compatible {
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bool enhance_rx;
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bool support_64g;
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bool use_internal_cd;
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+ bool mips_mt762x;
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};
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struct msdc_tune_para {
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@@ -547,6 +553,7 @@ static const struct mtk_mmc_compatible m
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.stop_clk_fix = false,
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.enhance_rx = false,
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.use_internal_cd = true,
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+ .mips_mt762x = true,
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};
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static const struct mtk_mmc_compatible mt7622_compat = {
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@@ -975,7 +982,12 @@ static void msdc_set_mclk(struct msdc_ho
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* mmc_select_hs400() will drop to 50Mhz and High speed mode,
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* tune result of hs200/200Mhz is not suitable for 50Mhz
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*/
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- if (mmc->actual_clock <= 52000000) {
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+ if (host->dev_comp->mips_mt762x &&
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+ mmc->actual_clock > 25000000) {
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+ sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
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+ sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
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+ sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
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+ } else if (mmc->actual_clock <= 52000000) {
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writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
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if (host->top_base) {
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writel(host->def_tune_para.emmc_top_control,
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@@ -1856,6 +1868,18 @@ static void msdc_init_hw(struct msdc_hos
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MSDC_PAD_TUNE_RXDLYSEL);
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}
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+ if (host->dev_comp->mips_mt762x) {
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+ /* Set pins drive strength */
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+ writel(0x000d0044, host->base + MSDC_PAD_CTRL0);
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+ writel(0x000e0044, host->base + MSDC_PAD_CTRL1);
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+ writel(0x000e0044, host->base + MSDC_PAD_CTRL2);
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+
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+ /* Set tuning parameters */
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+ writel(0x84101010, host->base + tune_reg);
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+ writel(0x10101010, host->base + MSDC_DAT_RDDLY0);
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+ writel(0x10101010, host->base + MSDC_DAT_RDDLY1);
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+ }
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+
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if (mmc->caps2 & MMC_CAP2_NO_SDIO) {
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sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
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sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
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