8c14f33bb4
The original PCS driver did not use the .pcs_validate() in phylink_pcs_ops. The patches for 1000/2500base-x and 10g modes were taken from this old driver, and thus did not bother with .pcs_validate(). Thus, even though these modes are supported, phylink would not enable them. To fix these, list these modes in .pcs_validate(). Also list them in ipq_pcs_clk_rate_get(). While the latter does not appear to change behavior, it does change the clock rates listed under /sys/kernel/debug/clk Co-developed-by: Mantas Pucka <mantas@8devices.com> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Link: https://github.com/openwrt/openwrt/pull/18435 Signed-off-by: Robert Marko <robimarko@gmail.com>
152 lines
4.3 KiB
Diff
152 lines
4.3 KiB
Diff
From e770b36f0353fd11c4628360fe412acb7f02f346 Mon Sep 17 00:00:00 2001
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From: Lei Wei <quic_leiwei@quicinc.com>
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Date: Wed, 6 Mar 2024 17:40:52 +0800
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Subject: [PATCH] net: pcs: Add 10GBASER interface mode support to IPQ UNIPHY
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PCS driver
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10GBASER mode is used when PCS connects with a 10G SFP module.
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Change-Id: Ifc3c3bb23811807a9b34e88771aab2c830c2327c
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Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
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Alex G: Use regmap to read/write registers
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Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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---
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drivers/net/pcs/pcs-qcom-ipq9574.c | 57 ++++++++++++++++++++++++++++++
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1 file changed, 57 insertions(+)
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--- a/drivers/net/pcs/pcs-qcom-ipq9574.c
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+++ b/drivers/net/pcs/pcs-qcom-ipq9574.c
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@@ -60,6 +60,9 @@
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FIELD_PREP(GENMASK(9, 2), \
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FIELD_GET(XPCS_INDIRECT_ADDR_L, reg)))
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+#define XPCS_10GBASER_STS 0x30020
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+#define XPCS_10GBASER_LINK_STS BIT(12)
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+
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#define XPCS_DIG_CTRL 0x38000
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#define XPCS_USXG_ADPT_RESET BIT(10)
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#define XPCS_USXG_EN BIT(9)
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@@ -229,6 +232,28 @@ static void ipq_pcs_get_state_usxgmii(st
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state->duplex = DUPLEX_FULL;
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}
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+static void ipq_unipcs_get_state_10gbaser(struct ipq_pcs *qpcs,
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+ struct phylink_link_state *state)
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+{
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+ unsigned int val;
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+ int ret;
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+
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+ ret = regmap_read(qpcs->regmap, XPCS_10GBASER_STS, &val);
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+ if (ret) {
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+ state->link = 0;
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+ return;
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+ }
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+
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+ state->link = !!(val & XPCS_10GBASER_LINK_STS);
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+
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+ if (!state->link)
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+ return;
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+
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+ state->speed = SPEED_10000;
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+ state->duplex = DUPLEX_FULL;
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+ state->pause |= MLO_PAUSE_TXRX_MASK;
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+}
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+
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static int ipq_pcs_config_mode(struct ipq_pcs *qpcs,
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phy_interface_t interface)
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{
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@@ -251,6 +276,7 @@ static int ipq_pcs_config_mode(struct ip
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val = PCS_MODE_PSGMII;
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break;
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case PHY_INTERFACE_MODE_USXGMII:
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+ case PHY_INTERFACE_MODE_10GBASER:
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val = PCS_MODE_XPCS;
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rate = 312500000;
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break;
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@@ -355,6 +381,25 @@ static int ipq_pcs_config_usxgmii(struct
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return regmap_set_bits(qpcs->regmap, XPCS_MII_CTRL, XPCS_MII_AN_EN);
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}
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+static int ipq_unipcs_config_10gbaser(struct ipq_pcs *qpcs,
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+ phy_interface_t interface)
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+{
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+ int ret;
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+
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+ if (qpcs->interface != interface) {
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+ ret = ipq_pcs_config_mode(qpcs, interface);
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+ if (ret)
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+ return ret;
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+
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+ /* Deassert XPCS */
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+ reset_control_deassert(qpcs->reset[XPCS_RESET]);
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+
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+ qpcs->interface = interface;
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+ }
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+
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+ return 0;
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+}
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+
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static unsigned long ipq_unipcs_clock_rate_get_gmii(int speed)
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{
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unsigned long rate = 0;
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@@ -421,6 +466,7 @@ ipq_unipcs_link_up_clock_rate_set(struct
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rate = ipq_unipcs_clock_rate_get_gmii(speed);
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break;
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case PHY_INTERFACE_MODE_USXGMII:
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+ case PHY_INTERFACE_MODE_10GBASER:
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rate = ipq_unipcs_clock_rate_get_xgmii(speed);
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break;
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default:
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@@ -528,6 +574,7 @@ static int ipq_pcs_validate(struct phyli
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switch (state->interface) {
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_QSGMII:
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+ case PHY_INTERFACE_MODE_10GBASER:
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return 0;
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case PHY_INTERFACE_MODE_USXGMII:
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/* USXGMII only supports full duplex mode */
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@@ -546,6 +593,7 @@ static unsigned int ipq_pcs_inband_caps(
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_QSGMII:
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case PHY_INTERFACE_MODE_USXGMII:
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+ case PHY_INTERFACE_MODE_10GBASER:
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return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE;
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default:
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return 0;
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@@ -602,6 +650,9 @@ static void ipq_pcs_get_state(struct phy
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case PHY_INTERFACE_MODE_USXGMII:
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ipq_pcs_get_state_usxgmii(qpcs, state);
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break;
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+ case PHY_INTERFACE_MODE_10GBASER:
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+ ipq_unipcs_get_state_10gbaser(qpcs, state);
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+ break;
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default:
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break;
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}
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@@ -631,6 +682,8 @@ static int ipq_pcs_config(struct phylink
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return ipq_pcs_config_sgmii(qpcs, index, neg_mode, interface);
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case PHY_INTERFACE_MODE_USXGMII:
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return ipq_pcs_config_usxgmii(qpcs);
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+ case PHY_INTERFACE_MODE_10GBASER:
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+ return ipq_unipcs_config_10gbaser(qpcs, interface);
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default:
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dev_err(qpcs->dev,
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"interface %s not supported\n", phy_modes(interface));
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@@ -662,6 +715,9 @@ static void ipq_pcs_link_up(struct phyli
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case PHY_INTERFACE_MODE_USXGMII:
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ret = ipq_pcs_link_up_config_usxgmii(qpcs, speed);
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break;
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+ case PHY_INTERFACE_MODE_10GBASER:
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+ /* Nothing to do here */
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+ break;
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default:
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dev_err(qpcs->dev,
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"interface %s not supported\n", phy_modes(interface));
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@@ -730,6 +786,7 @@ static unsigned long ipq_pcs_clk_rate_ge
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{
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switch (qpcs->interface) {
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case PHY_INTERFACE_MODE_USXGMII:
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+ case PHY_INTERFACE_MODE_10GBASER:
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return 312500000;
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default:
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return 125000000;
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