ebfd69a3e3
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.12.32 All patches are automatically refreshed. Signed-off-by: Shiji Yang <yangshiji66@outlook.com> Tested-by: John Audia <therealgraysky@proton.me> Link: https://github.com/openwrt/openwrt/pull/19027 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
72 lines
2.3 KiB
Diff
72 lines
2.3 KiB
Diff
From bbf706ecfd4295d73c8217d5220573dd51d7a081 Mon Sep 17 00:00:00 2001
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From: Luo Jie <quic_luoj@quicinc.com>
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Date: Fri, 1 Mar 2024 14:46:45 +0800
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Subject: [PATCH] arm64: dts: qcom: Add IPQ9574 PPE base device node
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PPE is the packet process engine on the Qualcomm IPQ platform,
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which is connected with the external switch or PHY device via
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the UNIPHY (PCS).
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Change-Id: I254bd48c218aa4eab54f697a2ad149f5a93b682c
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Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
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Alex G: Add "qcom_ppe" label to PPE node
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Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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---
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arch/arm64/boot/dts/qcom/ipq9574.dtsi | 39 +++++++++++++++++++++++++++
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1 file changed, 39 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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@@ -13,6 +13,7 @@
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#include <dt-bindings/interconnect/qcom,ipq9574.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
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+#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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@@ -1271,6 +1272,44 @@
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#interconnect-cells = <1>;
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};
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+ qcom_ppe: ethernet@3a000000 {
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+ compatible = "qcom,ipq9574-ppe";
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+ reg = <0x3a000000 0xbef800>;
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+ ranges;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ clocks = <&nsscc NSS_CC_PPE_SWITCH_CLK>,
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+ <&nsscc NSS_CC_PPE_SWITCH_CFG_CLK>,
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+ <&nsscc NSS_CC_PPE_SWITCH_IPE_CLK>,
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+ <&nsscc NSS_CC_PPE_SWITCH_BTQ_CLK>;
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+ clock-names = "ppe",
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+ "ppe_cfg",
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+ "ppe_ipe",
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+ "ppe_btq";
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+ resets = <&nsscc PPE_FULL_RESET>;
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+ interconnects = <&nsscc MASTER_NSSNOC_PPE
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+ &nsscc SLAVE_NSSNOC_PPE>,
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+ <&nsscc MASTER_NSSNOC_PPE_CFG
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+ &nsscc SLAVE_NSSNOC_PPE_CFG>,
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+ <&gcc MASTER_NSSNOC_QOSGEN_REF
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+ &gcc SLAVE_NSSNOC_QOSGEN_REF>,
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+ <&gcc MASTER_NSSNOC_TIMEOUT_REF
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+ &gcc SLAVE_NSSNOC_TIMEOUT_REF>,
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+ <&gcc MASTER_MEM_NOC_NSSNOC
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+ &gcc SLAVE_MEM_NOC_NSSNOC>,
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+ <&gcc MASTER_NSSNOC_MEMNOC
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+ &gcc SLAVE_NSSNOC_MEMNOC>,
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+ <&gcc MASTER_NSSNOC_MEM_NOC_1
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+ &gcc SLAVE_NSSNOC_MEM_NOC_1>;
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+ interconnect-names = "ppe",
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+ "ppe_cfg",
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+ "qos_gen",
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+ "timeout_ref",
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+ "nssnoc_memnoc",
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+ "memnoc_nssnoc",
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+ "memnoc_nssnoc_1";
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+ };
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+
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pcs_uniphy0: ethernet-pcs@7a00000 {
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compatible = "qcom,ipq9574-pcs";
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reg = <0x7a00000 0x10000>;
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