cd9f3b8d33
Add v3 submission of the qualcomm PPE driver. As of this writing, it is the latest version. This lacks the EDMA driver and network device support. That will be added in part 2. Link: https://lore.kernel.org/lkml/20250209-qcom_ipq_ppe-v3-0-453ea18d3271@quicinc.com Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Link: https://github.com/openwrt/openwrt/pull/18796 Signed-off-by: Robert Marko <robimarko@gmail.com>
122 lines
4.1 KiB
Diff
122 lines
4.1 KiB
Diff
From c4a321bc120fabc318df165a7fcdeddfcf052253 Mon Sep 17 00:00:00 2001
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From: Luo Jie <quic_luoj@quicinc.com>
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Date: Sun, 9 Feb 2025 22:29:45 +0800
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Subject: [PATCH] net: ethernet: qualcomm: Initialize PPE queue to Ethernet DMA
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ring mapping
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Configure the selected queues to map with an Ethernet DMA ring for the
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packet to receive on ARM cores.
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As default initialization, all queues assigned to CPU port 0 are mapped
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to the EDMA ring 0. This configuration is later updated during Ethernet
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DMA initialization.
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Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
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---
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.../net/ethernet/qualcomm/ppe/ppe_config.c | 47 ++++++++++++++++++-
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.../net/ethernet/qualcomm/ppe/ppe_config.h | 6 +++
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drivers/net/ethernet/qualcomm/ppe/ppe_regs.h | 5 ++
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3 files changed, 57 insertions(+), 1 deletion(-)
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--- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.c
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+++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.c
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@@ -1328,6 +1328,28 @@ int ppe_rss_hash_config_set(struct ppe_d
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return 0;
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}
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+/**
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+ * ppe_ring_queue_map_set - Set the PPE queue to Ethernet DMA ring mapping
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+ * @ppe_dev: PPE device
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+ * @ring_id: Ethernet DMA ring ID
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+ * @queue_map: Bit map of queue IDs to given Ethernet DMA ring
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+ *
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+ * Configure the mapping from a set of PPE queues to a given Ethernet DMA ring.
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+ *
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+ * Return: 0 on success, negative error code on failure.
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+ */
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+int ppe_ring_queue_map_set(struct ppe_device *ppe_dev, int ring_id, u32 *queue_map)
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+{
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+ u32 reg, queue_bitmap_val[PPE_RING_TO_QUEUE_BITMAP_WORD_CNT];
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+
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+ memcpy(queue_bitmap_val, queue_map, sizeof(queue_bitmap_val));
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+ reg = PPE_RING_Q_MAP_TBL_ADDR + PPE_RING_Q_MAP_TBL_INC * ring_id;
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+
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+ return regmap_bulk_write(ppe_dev->regmap, reg,
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+ queue_bitmap_val,
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+ ARRAY_SIZE(queue_bitmap_val));
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+}
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+
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static int ppe_config_bm_threshold(struct ppe_device *ppe_dev, int bm_port_id,
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const struct ppe_bm_port_config port_cfg)
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{
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@@ -1847,6 +1869,25 @@ static int ppe_rss_hash_init(struct ppe_
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return ppe_rss_hash_config_set(ppe_dev, PPE_RSS_HASH_MODE_IPV6, hash_cfg);
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}
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+/* Initialize mapping between PPE queues assigned to CPU port 0
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+ * to Ethernet DMA ring 0.
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+ */
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+static int ppe_queues_to_ring_init(struct ppe_device *ppe_dev)
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+{
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+ u32 queue_bmap[PPE_RING_TO_QUEUE_BITMAP_WORD_CNT] = {};
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+ int ret, queue_id, queue_max;
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+
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+ ret = ppe_port_resource_get(ppe_dev, 0, PPE_RES_UCAST,
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+ &queue_id, &queue_max);
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+ if (ret)
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+ return ret;
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+
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+ for (; queue_id <= queue_max; queue_id++)
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+ queue_bmap[queue_id / 32] |= BIT_MASK(queue_id % 32);
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+
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+ return ppe_ring_queue_map_set(ppe_dev, 0, queue_bmap);
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+}
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+
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int ppe_hw_config(struct ppe_device *ppe_dev)
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{
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int ret;
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@@ -1875,5 +1916,9 @@ int ppe_hw_config(struct ppe_device *ppe
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if (ret)
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return ret;
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- return ppe_rss_hash_init(ppe_dev);
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+ ret = ppe_rss_hash_init(ppe_dev);
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+ if (ret)
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+ return ret;
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+
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+ return ppe_queues_to_ring_init(ppe_dev);
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}
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--- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.h
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+++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.h
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@@ -29,6 +29,9 @@
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#define PPE_RSS_HASH_IP_LENGTH 4
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#define PPE_RSS_HASH_TUPLES 5
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+/* PPE supports 300 queues, each bit presents as one queue. */
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+#define PPE_RING_TO_QUEUE_BITMAP_WORD_CNT 10
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+
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/**
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* enum ppe_scheduler_frame_mode - PPE scheduler frame mode.
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* @PPE_SCH_WITH_IPG_PREAMBLE_FRAME_CRC: The scheduled frame includes IPG,
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@@ -308,4 +311,7 @@ int ppe_sc_config_set(struct ppe_device
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int ppe_counter_enable_set(struct ppe_device *ppe_dev, int port);
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int ppe_rss_hash_config_set(struct ppe_device *ppe_dev, int mode,
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struct ppe_rss_hash_cfg hash_cfg);
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+int ppe_ring_queue_map_set(struct ppe_device *ppe_dev,
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+ int ring_id,
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+ u32 *queue_map);
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#endif
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--- a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h
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+++ b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h
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@@ -207,6 +207,11 @@
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#define PPE_L0_COMP_CFG_TBL_SHAPER_METER_LEN GENMASK(1, 0)
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#define PPE_L0_COMP_CFG_TBL_NODE_METER_LEN GENMASK(3, 2)
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+/* PPE queue to Ethernet DMA ring mapping table. */
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+#define PPE_RING_Q_MAP_TBL_ADDR 0x42a000
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+#define PPE_RING_Q_MAP_TBL_ENTRIES 24
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+#define PPE_RING_Q_MAP_TBL_INC 0x40
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+
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/* Table addresses for per-queue dequeue setting. */
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#define PPE_DEQ_OPR_TBL_ADDR 0x430000
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#define PPE_DEQ_OPR_TBL_ENTRIES 300
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