3744b73602
Add the v5 of the PCS patch. This is the latest submission as of this writing. THe last four patches are not part of the submission. They make the series work with v6.12 kernel, resolve a circular dependency with the clocks, and add the DTS node. Include them as bundle. Link: https://lore.kernel.org/lkml/20250207-ipq_pcs_6-14_rc1-v5-0-be2ebec32921@quicinc.com/ Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Link: https://github.com/openwrt/openwrt/pull/18796 Signed-off-by: Robert Marko <robimarko@gmail.com>
234 lines
8.3 KiB
Diff
234 lines
8.3 KiB
Diff
From 5f650721c4b232a14a1a3e25b686f2234faee961 Mon Sep 17 00:00:00 2001
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From: Lei Wei <quic_leiwei@quicinc.com>
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Date: Fri, 7 Feb 2025 23:53:12 +0800
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Subject: [PATCH] dt-bindings: net: pcs: Add Ethernet PCS for Qualcomm IPQ9574
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SoC
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The 'UNIPHY' PCS block in the IPQ9574 SoC includes PCS and SerDes
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functions. It supports different interface modes to enable Ethernet
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MAC connections to different types of external PHYs/switch. It includes
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PCS functions for 1Gbps and 2.5Gbps interface modes and XPCS functions
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for 10Gbps interface modes. There are three UNIPHY (PCS) instances
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in IPQ9574 SoC which provide PCS/XPCS functions to the six Ethernet
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ports.
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Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
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---
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.../bindings/net/pcs/qcom,ipq9574-pcs.yaml | 190 ++++++++++++++++++
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include/dt-bindings/net/qcom,ipq9574-pcs.h | 15 ++
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2 files changed, 205 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/net/pcs/qcom,ipq9574-pcs.yaml
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create mode 100644 include/dt-bindings/net/qcom,ipq9574-pcs.h
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/net/pcs/qcom,ipq9574-pcs.yaml
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@@ -0,0 +1,190 @@
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/net/pcs/qcom,ipq9574-pcs.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: Ethernet PCS for Qualcomm IPQ9574 SoC
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+
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+maintainers:
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+ - Lei Wei <quic_leiwei@quicinc.com>
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+
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+description:
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+ The UNIPHY hardware blocks in the Qualcomm IPQ SoC include PCS and SerDes
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+ functions. They enable connectivity between the Ethernet MAC inside the
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+ PPE (packet processing engine) and external Ethernet PHY/switch. There are
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+ three UNIPHY instances in IPQ9574 SoC which provide PCS functions to the
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+ six Ethernet ports.
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+
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+ For SGMII (1Gbps PHY) or 2500BASE-X (2.5Gbps PHY) interface modes, the PCS
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+ function is enabled by using the PCS block inside UNIPHY. For USXGMII (10Gbps
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+ PHY), the XPCS block in UNIPHY is used.
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+
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+ The SerDes provides 125M (1Gbps mode) or 312.5M (2.5Gbps and 10Gbps modes)
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+ RX and TX clocks to the NSSCC (Networking Sub System Clock Controller). The
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+ NSSCC divides these clocks and generates the MII RX and TX clocks to each
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+ of the MII interfaces between the PCS and MAC, as per the link speeds and
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+ interface modes.
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+
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+ Different IPQ SoC may support different number of UNIPHYs (PCSes) since the
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+ number of ports and their capabilities can be different between these SoCs
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+
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+ Below diagram depicts the UNIPHY (PCS) connections for an IPQ9574 SoC based
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+ board. In this example, the PCS0 has four GMIIs/XGMIIs, which can connect
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+ with four MACs to support QSGMII (4 x 1Gbps) or 10G_QXGMII (4 x 2.5Gbps)
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+ interface modes.
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+
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+ - +-------+ +---------+ +-------------------------+
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+ +---------+CMN PLL| | GCC | | NSSCC (Divider) |
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+ | +----+--+ +----+----+ +--+-------+--------------+
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+ | | | ^ |
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+ | 31.25M | SYS/AHB|clk RX/TX|clk +------------+
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+ | ref clk| | | | |
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+ | | v | MII RX|TX clk MAC| RX/TX clk
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+ |25/50M +--+---------+----------+-------+---+ +-+---------+
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+ |ref clk | | +----------------+ | | | | PPE |
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+ v | | | UNIPHY0 V | | V |
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+ +-------+ | v | +-----------+ (X)GMII| | |
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+ | | | +---+---+ | |--------|------|-- MAC0 |
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+ | | | | | | | (X)GMII| | |
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+ | Quad | | |SerDes | | PCS/XPCS |--------|------|-- MAC1 |
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+ | +<----+ | | | | (X)GMII| | |
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+ |(X)GPHY| | | | | |--------|------|-- MAC2 |
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+ | | | | | | | (X)GMII| | |
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+ | | | +-------+ | |--------|------|-- MAC3 |
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+ +-------+ | | | | | |
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+ | +-----------+ | | |
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+ +-----------------------------------+ | |
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+ +--+---------+----------+-------+---+ | |
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+ +-------+ | UNIPHY1 | | |
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+ | | | +-----------+ | | |
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+ |(X)GPHY| | +-------+ | | (X)GMII| | |
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+ | +<----+ |SerDes | | PCS/XPCS |--------|------|- MAC4 |
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+ | | | | | | | | | |
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+ +-------+ | +-------+ | | | | |
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+ | +-----------+ | | |
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+ +-----------------------------------+ | |
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+ +--+---------+----------+-------+---+ | |
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+ +-------+ | UNIPHY2 | | |
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+ | | | +-----------+ | | |
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+ |(X)GPHY| | +-------+ | | (X)GMII| | |
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+ | +<----+ |SerDes | | PCS/XPCS |--------|------|- MAC5 |
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+ | | | | | | | | | |
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+ +-------+ | +-------+ | | | | |
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+ | +-----------+ | | |
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+ +-----------------------------------+ +-----------+
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+
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+properties:
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+ compatible:
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+ enum:
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+ - qcom,ipq9574-pcs
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+
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+ reg:
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+ maxItems: 1
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+
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+ '#address-cells':
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+ const: 1
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+
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+ '#size-cells':
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+ const: 0
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+
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+ clocks:
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+ items:
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+ - description: System clock
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+ - description: AHB clock needed for register interface access
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+
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+ clock-names:
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+ items:
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+ - const: sys
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+ - const: ahb
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+
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+ '#clock-cells':
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+ const: 1
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+ description: See include/dt-bindings/net/qcom,ipq9574-pcs.h for constants
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+
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+patternProperties:
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+ '^pcs-mii@[0-4]$':
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+ type: object
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+ description: PCS MII interface.
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+
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+ properties:
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+ reg:
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+ minimum: 0
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+ maximum: 4
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+ description: MII index
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+
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+ clocks:
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+ items:
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+ - description: PCS MII RX clock
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+ - description: PCS MII TX clock
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+
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+ clock-names:
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+ items:
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+ - const: rx
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+ - const: tx
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+
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+ required:
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+ - reg
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+ - clocks
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+ - clock-names
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+
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+ additionalProperties: false
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+
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+required:
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+ - compatible
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+ - reg
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+ - '#address-cells'
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+ - '#size-cells'
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+ - clocks
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+ - clock-names
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+ - '#clock-cells'
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
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+
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+ ethernet-pcs@7a00000 {
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+ compatible = "qcom,ipq9574-pcs";
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+ reg = <0x7a00000 0x10000>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ clocks = <&gcc GCC_UNIPHY0_SYS_CLK>,
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+ <&gcc GCC_UNIPHY0_AHB_CLK>;
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+ clock-names = "sys",
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+ "ahb";
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+ #clock-cells = <1>;
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+
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+ pcs-mii@0 {
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+ reg = <0>;
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+ clocks = <&nsscc 116>,
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+ <&nsscc 117>;
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+ clock-names = "rx",
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+ "tx";
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+ };
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+
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+ pcs-mii@1 {
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+ reg = <1>;
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+ clocks = <&nsscc 118>,
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+ <&nsscc 119>;
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+ clock-names = "rx",
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+ "tx";
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+ };
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+
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+ pcs-mii@2 {
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+ reg = <2>;
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+ clocks = <&nsscc 120>,
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+ <&nsscc 121>;
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+ clock-names = "rx",
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+ "tx";
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+ };
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+
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+ pcs-mii@3 {
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+ reg = <3>;
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+ clocks = <&nsscc 122>,
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+ <&nsscc 123>;
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+ clock-names = "rx",
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+ "tx";
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+ };
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+ };
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--- /dev/null
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+++ b/include/dt-bindings/net/qcom,ipq9574-pcs.h
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@@ -0,0 +1,15 @@
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+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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+/*
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+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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+ *
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+ * Device Tree constants for the Qualcomm IPQ9574 PCS
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+ */
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+
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+#ifndef _DT_BINDINGS_PCS_QCOM_IPQ9574_H
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+#define _DT_BINDINGS_PCS_QCOM_IPQ9574_H
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+
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+/* The RX and TX clocks which are provided from the SerDes to NSSCC. */
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+#define PCS_RX_CLK 0
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+#define PCS_TX_CLK 1
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+
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+#endif /* _DT_BINDINGS_PCS_QCOM_IPQ9574_H */
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