390e516a3b
This driver is cherry-picked from target/linux/qualcommbe/patches-6.6. While Qualcomm did submit past patches for QCA8084, the code has since ben split from at803x. The existing OpenWRT version of the patch is the cleanest version I could find. Add it here. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Link: https://github.com/openwrt/openwrt/pull/18796 Signed-off-by: Robert Marko <robimarko@gmail.com>
90 lines
2.8 KiB
Diff
90 lines
2.8 KiB
Diff
From d1f2a1810af1833196934977f57607432fda46b4 Mon Sep 17 00:00:00 2001
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From: Luo Jie <quic_luoj@quicinc.com>
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Date: Wed, 8 Nov 2023 18:01:14 +0800
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Subject: [PATCH] net: phy: qca808x: Add link_change_notify function for
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QCA8084
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When the link is changed, QCA8084 needs to do the fifo reset and
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adjust the IPG level for the 10G-QXGMII link on the speed 1000M.
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Change-Id: I21de802c78496fb95f1c5119fe3894c9fdebbd65
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Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
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---
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drivers/net/phy/qcom/qca808x.c | 52 ++++++++++++++++++++++++++++++++++
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1 file changed, 52 insertions(+)
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--- a/drivers/net/phy/qcom/qca808x.c
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+++ b/drivers/net/phy/qcom/qca808x.c
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@@ -103,6 +103,14 @@
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#define QCA8084_MSE_THRESHOLD 0x800a
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#define QCA8084_MSE_THRESHOLD_2P5G_VAL 0x51c6
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+/* QCA8084 FIFO reset control */
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+#define QCA8084_FIFO_CONTROL 0x19
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+#define QCA8084_FIFO_MAC_2_PHY BIT(1)
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+#define QCA8084_FIFO_PHY_2_MAC BIT(0)
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+
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+#define QCA8084_MMD7_IPG_OP 0x901d
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+#define QCA8084_IPG_10_TO_11_EN BIT(0)
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+
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MODULE_DESCRIPTION("Qualcomm Atheros QCA808X PHY driver");
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MODULE_AUTHOR("Matus Ujhelyi, Luo Jie");
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MODULE_LICENSE("GPL");
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@@ -697,6 +705,49 @@ static int qca8084_config_init(struct ph
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QCA8084_MSE_THRESHOLD_2P5G_VAL);
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}
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+static void qca8084_link_change_notify(struct phy_device *phydev)
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+{
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+ int ret;
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+
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+ /* Assert the FIFO between PHY and MAC. */
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+ ret = phy_modify(phydev, QCA8084_FIFO_CONTROL,
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+ QCA8084_FIFO_MAC_2_PHY | QCA8084_FIFO_PHY_2_MAC,
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+ 0);
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+ if (ret) {
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+ phydev_err(phydev, "Asserting PHY FIFO failed\n");
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+ return;
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+ }
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+
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+ /* If the PHY is in 10G_QXGMII mode, the FIFO needs to be kept in
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+ * reset state when link is down, otherwise the FIFO needs to be
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+ * de-asserted after waiting 50 ms to make the assert completed.
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+ */
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+ if (phydev->interface != PHY_INTERFACE_MODE_10G_QXGMII ||
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+ phydev->link) {
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+ msleep(50);
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+
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+ /* Deassert the FIFO between PHY and MAC. */
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+ ret = phy_modify(phydev, QCA8084_FIFO_CONTROL,
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+ QCA8084_FIFO_MAC_2_PHY |
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+ QCA8084_FIFO_PHY_2_MAC,
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+ QCA8084_FIFO_MAC_2_PHY |
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+ QCA8084_FIFO_PHY_2_MAC);
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+ if (ret) {
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+ phydev_err(phydev, "De-asserting PHY FIFO failed\n");
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+ return;
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+ }
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+ }
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+
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+ /* Enable IPG level 10 to 11 tuning for link speed 1000M in the
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+ * 10G_QXGMII mode.
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+ */
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+ if (phydev->interface == PHY_INTERFACE_MODE_10G_QXGMII)
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+ phy_modify_mmd(phydev, MDIO_MMD_AN, QCA8084_MMD7_IPG_OP,
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+ QCA8084_IPG_10_TO_11_EN,
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+ phydev->speed == SPEED_1000 ?
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+ QCA8084_IPG_10_TO_11_EN : 0);
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+}
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+
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static struct phy_driver qca808x_driver[] = {
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{
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/* Qualcomm QCA8081 */
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@@ -746,6 +797,7 @@ static struct phy_driver qca808x_driver[
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.cable_test_start = qca808x_cable_test_start,
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.cable_test_get_status = qca808x_cable_test_get_status,
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.config_init = qca8084_config_init,
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+ .link_change_notify = qca8084_link_change_notify,
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}, };
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module_phy_driver(qca808x_driver);
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