a8feb51e71
This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Tim Harvey <tharvey@gateworks.com> Link: https://github.com/openwrt/openwrt/pull/19029 Signed-off-by: Nick Hainke <vincent@systemli.org>
121 lines
4 KiB
Diff
121 lines
4 KiB
Diff
From cf983e4a04eecb5be93af7b53cb10805ee448998 Mon Sep 17 00:00:00 2001
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From: Tim Harvey <tharvey@gateworks.com>
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Date: Mon, 21 Aug 2023 09:20:17 -0700
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Subject: [PATCH] PCI: imx6: Start link at max gen first for IMX8MM and IMX8MP
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commit fa33a6d87eac ("PCI: imx6: Start link in Gen1 before negotiating
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for Gen2 mode") started link negotiation at Gen1 before attempting
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faster speeds in order to work around an issue with a particular switch
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on an IMX6Q SoC.
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This behavior is not the norm for PCI link negotiation and it has been
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found to cause issues in other cases:
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- IMX8MM with PI7C9X2G608GP switch: various endpoints (such as qca988x)
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will fail to link more than 50% of the time
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- IMX8MP with PI7C9X2G608GP switch: occasionally will fail to link with
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switch and cause a CPU hang about 30% of the time
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Disable this behavior for IMX8MM and IMX8MP.
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Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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---
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drivers/pci/controller/dwc/pci-imx6.c | 53 ++++++++++++++-------------
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1 file changed, 27 insertions(+), 26 deletions(-)
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--- a/drivers/pci/controller/dwc/pci-imx6.c
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+++ b/drivers/pci/controller/dwc/pci-imx6.c
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@@ -60,6 +60,7 @@ enum imx6_pcie_variants {
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#define IMX6_PCIE_FLAG_IMX6_PHY BIT(0)
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#define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1)
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#define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2)
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+#define IMX6_PCIE_FLAG_GEN1_LAST BIT(3)
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#define IMX6_PCIE_MAX_CLKS 6
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@@ -836,26 +837,28 @@ static int imx6_pcie_start_link(struct d
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u32 tmp;
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int ret;
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- /*
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- * Force Gen1 operation when starting the link. In case the link is
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- * started in Gen2 mode, there is a possibility the devices on the
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- * bus will not be detected at all. This happens with PCIe switches.
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- */
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- dw_pcie_dbi_ro_wr_en(pci);
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- tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
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- tmp &= ~PCI_EXP_LNKCAP_SLS;
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- tmp |= PCI_EXP_LNKCAP_SLS_2_5GB;
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- dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp);
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- dw_pcie_dbi_ro_wr_dis(pci);
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+ if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_GEN1_LAST)) {
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+ /*
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+ * Force Gen1 operation when starting the link. In case the link is
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+ * started in Gen2 mode, there is a possibility the devices on the
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+ * bus will not be detected at all. This happens with PCIe switches.
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+ */
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+ dw_pcie_dbi_ro_wr_en(pci);
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+ tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
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+ tmp &= ~PCI_EXP_LNKCAP_SLS;
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+ tmp |= PCI_EXP_LNKCAP_SLS_2_5GB;
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+ dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp);
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+ dw_pcie_dbi_ro_wr_dis(pci);
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+ }
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/* Start LTSSM. */
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imx6_pcie_ltssm_enable(dev);
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- ret = dw_pcie_wait_for_link(pci);
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- if (ret)
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- goto err_reset_phy;
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+ if ((pci->link_gen > 1) && !(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_GEN1_LAST)) {
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+ ret = dw_pcie_wait_for_link(pci);
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+ if (ret)
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+ goto err_reset_phy;
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- if (pci->link_gen > 1) {
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/* Allow faster modes after the link is up */
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dw_pcie_dbi_ro_wr_en(pci);
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tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
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@@ -889,18 +892,14 @@ static int imx6_pcie_start_link(struct d
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goto err_reset_phy;
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}
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}
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-
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- /* Make sure link training is finished as well! */
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- ret = dw_pcie_wait_for_link(pci);
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- if (ret)
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- goto err_reset_phy;
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- } else {
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- dev_info(dev, "Link: Only Gen1 is enabled\n");
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}
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+ ret = dw_pcie_wait_for_link(pci);
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+ if (ret)
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+ goto err_reset_phy;
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+
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imx6_pcie->link_is_up = true;
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- tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);
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- dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS);
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+
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return 0;
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err_reset_phy:
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@@ -1457,14 +1456,16 @@ static const struct imx6_pcie_drvdata dr
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},
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[IMX8MM] = {
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.variant = IMX8MM,
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- .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
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+ .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND |
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+ IMX6_PCIE_FLAG_GEN1_LAST,
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.gpr = "fsl,imx8mm-iomuxc-gpr",
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.clk_names = imx8mm_clks,
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.clks_cnt = ARRAY_SIZE(imx8mm_clks),
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},
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[IMX8MP] = {
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.variant = IMX8MP,
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- .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
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+ .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND |
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+ IMX6_PCIE_FLAG_GEN1_LAST,
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.gpr = "fsl,imx8mp-iomuxc-gpr",
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.clk_names = imx8mm_clks,
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.clks_cnt = ARRAY_SIZE(imx8mm_clks),
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