a8feb51e71
This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Tim Harvey <tharvey@gateworks.com> Link: https://github.com/openwrt/openwrt/pull/19029 Signed-off-by: Nick Hainke <vincent@systemli.org>
39 lines
1.1 KiB
Diff
39 lines
1.1 KiB
Diff
From 6cea7c46172eca323e9ce7e6aab8f8506eb92b4b Mon Sep 17 00:00:00 2001
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From: Tim Harvey <tharvey@gateworks.com>
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Date: Wed, 29 Nov 2023 09:53:04 -0800
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Subject: [PATCH 405/413] 6.9: arm64: dts: imx8mm-venice-gw71xx: add TPM device
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Add the TPM device found on the GW71xx revision E PCB.
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Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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---
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.../arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi | 10 +++++++++-
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1 file changed, 9 insertions(+), 1 deletion(-)
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--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
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+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
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@@ -53,8 +53,15 @@
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&ecspi2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi2>;
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- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
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+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
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+ <&gpio1 10 GPIO_ACTIVE_LOW>;
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status = "okay";
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+
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+ tpm@1 {
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+ compatible = "tcg,tpm_tis-spi";
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+ reg = <0x1>;
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+ spi-max-frequency = <36000000>;
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+ };
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};
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&gpio1 {
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@@ -201,6 +208,7 @@
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MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
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MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
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MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
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+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6
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>;
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};
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