be3ce63822
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.12.36 Remove upstream patches: generic/backport-6.12/780-09-v6.13-r8169-add-support-for-RTL8125D.patch[1] generic/backport-6.12/781-04-v6.13-net-phy-realtek-merge-the-drivers-for-internal-NBase.patch[2] generic/backport-6.12/781-05-v6.13-net-phy-realtek-add-RTL8125D-internal-PHY.patch[3] All other patches are automatically refreshed. [1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.12.36&id=37cb5967bd2513416398ff1a87a5ee2e63270b00 [2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.12.36&id=5eb0b10eea271e2e1f7d4fa1a6af6c09b2ecc4f5 [3] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.12.36&id=5d479182d4ccde76df830a72927b3bdaafd142bf Signed-off-by: Shiji Yang <yangshiji66@outlook.com> Tested-by: John Audia <therealgraysky@proton.me> Link: https://github.com/openwrt/openwrt/pull/19317 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
106 lines
3 KiB
Diff
106 lines
3 KiB
Diff
From 081c9c0265c91b8333165aa6230c20bcbc6f7cbf Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Thu, 10 Oct 2024 14:07:16 +0100
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Subject: [PATCH] net: phy: realtek: read duplex and gbit master from PHYSR
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register
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The PHYSR MMD register is present and defined equally for all RTL82xx
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Ethernet PHYs.
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Read duplex and Gbit master bits from rtlgen_decode_speed() and rename
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it to rtlgen_decode_physr().
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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Link: https://patch.msgid.link/b9a76341da851a18c985bc4774fa295babec79bb.1728565530.git.daniel@makrotopia.org
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Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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---
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drivers/net/phy/realtek.c | 41 +++++++++++++++++++++++++++++++--------
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1 file changed, 33 insertions(+), 8 deletions(-)
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--- a/drivers/net/phy/realtek.c
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+++ b/drivers/net/phy/realtek.c
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@@ -80,15 +80,18 @@
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#define RTL822X_VND2_GANLPAR 0xa414
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-#define RTL822X_VND2_PHYSR 0xa434
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-
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#define RTL8366RB_POWER_SAVE 0x15
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#define RTL8366RB_POWER_SAVE_ON BIT(12)
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#define RTL9000A_GINMR 0x14
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#define RTL9000A_GINMR_LINK_STATUS BIT(4)
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-#define RTLGEN_SPEED_MASK 0x0630
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+#define RTL_VND2_PHYSR 0xa434
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+#define RTL_VND2_PHYSR_DUPLEX BIT(3)
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+#define RTL_VND2_PHYSR_SPEEDL GENMASK(5, 4)
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+#define RTL_VND2_PHYSR_SPEEDH GENMASK(10, 9)
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+#define RTL_VND2_PHYSR_MASTER BIT(11)
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+#define RTL_VND2_PHYSR_SPEED_MASK (RTL_VND2_PHYSR_SPEEDL | RTL_VND2_PHYSR_SPEEDH)
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#define RTL_GENERIC_PHYID 0x001cc800
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#define RTL_8211FVD_PHYID 0x001cc878
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@@ -661,9 +664,18 @@ static int rtl8366rb_config_init(struct
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}
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/* get actual speed to cover the downshift case */
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-static void rtlgen_decode_speed(struct phy_device *phydev, int val)
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+static void rtlgen_decode_physr(struct phy_device *phydev, int val)
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{
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- switch (val & RTLGEN_SPEED_MASK) {
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+ /* bit 3
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+ * 0: Half Duplex
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+ * 1: Full Duplex
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+ */
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+ if (val & RTL_VND2_PHYSR_DUPLEX)
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+ phydev->duplex = DUPLEX_FULL;
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+ else
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+ phydev->duplex = DUPLEX_HALF;
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+
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+ switch (val & RTL_VND2_PHYSR_SPEED_MASK) {
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case 0x0000:
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phydev->speed = SPEED_10;
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break;
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@@ -685,6 +697,19 @@ static void rtlgen_decode_speed(struct p
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default:
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break;
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}
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+
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+ /* bit 11
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+ * 0: Slave Mode
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+ * 1: Master Mode
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+ */
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+ if (phydev->speed >= 1000) {
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+ if (val & RTL_VND2_PHYSR_MASTER)
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+ phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
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+ else
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+ phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
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+ } else {
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+ phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
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+ }
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}
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static int rtlgen_read_status(struct phy_device *phydev)
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@@ -702,7 +727,7 @@ static int rtlgen_read_status(struct phy
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if (val < 0)
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return val;
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- rtlgen_decode_speed(phydev, val);
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+ rtlgen_decode_physr(phydev, val);
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return 0;
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}
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@@ -1008,11 +1033,11 @@ static int rtl822x_c45_read_status(struc
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return 0;
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/* Read actual speed from vendor register. */
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- val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL822X_VND2_PHYSR);
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+ val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_VND2_PHYSR);
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if (val < 0)
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return val;
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- rtlgen_decode_speed(phydev, val);
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+ rtlgen_decode_physr(phydev, val);
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return 0;
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}
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