0bd694ea22
Backport accepted BCM5325 patches from net-next. These patches will be merged in the v6.17 kernel window. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
128 lines
4 KiB
Diff
128 lines
4 KiB
Diff
From 651c9e71ffe44e99b5a9b011271c2117f0353b32 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
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Date: Sat, 14 Jun 2025 09:59:58 +0200
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Subject: [PATCH] net: dsa: b53: fix unicast/multicast flooding on BCM5325
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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BCM5325 doesn't implement UC_FLOOD_MASK, MC_FLOOD_MASK and IPMC_FLOOD_MASK
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registers.
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This has to be handled differently with other pages and registers.
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Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
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Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
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Link: https://patch.msgid.link/20250614080000.1884236-13-noltari@gmail.com
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/dsa/b53/b53_common.c | 60 ++++++++++++++++++++++----------
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drivers/net/dsa/b53/b53_regs.h | 13 +++++++
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2 files changed, 55 insertions(+), 18 deletions(-)
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--- a/drivers/net/dsa/b53/b53_common.c
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+++ b/drivers/net/dsa/b53/b53_common.c
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@@ -560,12 +560,24 @@ static void b53_port_set_ucast_flood(str
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{
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u16 uc;
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- b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc);
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- if (unicast)
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- uc |= BIT(port);
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- else
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- uc &= ~BIT(port);
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- b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc);
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+ if (is5325(dev)) {
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+ if (port == B53_CPU_PORT_25)
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+ port = B53_CPU_PORT;
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+
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+ b53_read16(dev, B53_IEEE_PAGE, B53_IEEE_UCAST_DLF, &uc);
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+ if (unicast)
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+ uc |= BIT(port) | B53_IEEE_UCAST_DROP_EN;
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+ else
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+ uc &= ~BIT(port);
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+ b53_write16(dev, B53_IEEE_PAGE, B53_IEEE_UCAST_DLF, uc);
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+ } else {
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+ b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc);
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+ if (unicast)
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+ uc |= BIT(port);
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+ else
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+ uc &= ~BIT(port);
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+ b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc);
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+ }
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}
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static void b53_port_set_mcast_flood(struct b53_device *dev, int port,
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@@ -573,19 +585,31 @@ static void b53_port_set_mcast_flood(str
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{
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u16 mc;
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- b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc);
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- if (multicast)
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- mc |= BIT(port);
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- else
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- mc &= ~BIT(port);
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- b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc);
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-
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- b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc);
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- if (multicast)
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- mc |= BIT(port);
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- else
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- mc &= ~BIT(port);
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- b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc);
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+ if (is5325(dev)) {
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+ if (port == B53_CPU_PORT_25)
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+ port = B53_CPU_PORT;
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+
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+ b53_read16(dev, B53_IEEE_PAGE, B53_IEEE_MCAST_DLF, &mc);
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+ if (multicast)
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+ mc |= BIT(port) | B53_IEEE_MCAST_DROP_EN;
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+ else
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+ mc &= ~BIT(port);
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+ b53_write16(dev, B53_IEEE_PAGE, B53_IEEE_MCAST_DLF, mc);
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+ } else {
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+ b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc);
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+ if (multicast)
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+ mc |= BIT(port);
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+ else
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+ mc &= ~BIT(port);
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+ b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc);
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+
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+ b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc);
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+ if (multicast)
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+ mc |= BIT(port);
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+ else
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+ mc &= ~BIT(port);
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+ b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc);
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+ }
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}
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static void b53_port_set_learning(struct b53_device *dev, int port,
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--- a/drivers/net/dsa/b53/b53_regs.h
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+++ b/drivers/net/dsa/b53/b53_regs.h
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@@ -29,6 +29,7 @@
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#define B53_ARLIO_PAGE 0x05 /* ARL Access */
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#define B53_FRAMEBUF_PAGE 0x06 /* Management frame access */
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#define B53_MEM_ACCESS_PAGE 0x08 /* Memory access */
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+#define B53_IEEE_PAGE 0x0a /* IEEE 802.1X */
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/* PHY Registers */
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#define B53_PORT_MII_PAGE(i) (0x10 + (i)) /* Port i MII Registers */
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@@ -369,6 +370,18 @@
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#define B53_ARL_SRCH_RSTL(x) (B53_ARL_SRCH_RSTL_0 + ((x) * 0x10))
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/*************************************************************************
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+ * IEEE 802.1X Registers
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+ *************************************************************************/
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+
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+/* Multicast DLF Drop Control register (16 bit) */
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+#define B53_IEEE_MCAST_DLF 0x94
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+#define B53_IEEE_MCAST_DROP_EN BIT(11)
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+
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+/* Unicast DLF Drop Control register (16 bit) */
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+#define B53_IEEE_UCAST_DLF 0x96
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+#define B53_IEEE_UCAST_DROP_EN BIT(11)
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+
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+/*************************************************************************
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* Port VLAN Registers
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*************************************************************************/
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