53c723246a
This is needed to restore compatibility with legacy brcmnand controllers. 3bfb22cecfe6 mtd: rawnand: brcmnand: legacy exec_op implementation 528b541b71cf mtd: nand: brcmnand: fix NAND timeout when accessing eMMC 56fce7547004 mtd: rawnand: brcmnand: remove unused parameters Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
30 lines
1.2 KiB
Diff
30 lines
1.2 KiB
Diff
From 528b541b71cf03e263272b051b70696f92258e9d Mon Sep 17 00:00:00 2001
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From: David Regan <dregan@broadcom.com>
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Date: Thu, 22 May 2025 10:25:17 -0700
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Subject: [PATCH] mtd: nand: brcmnand: fix NAND timeout when accessing eMMC
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When booting a board to NAND and accessing NAND while eMMC
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transactions are occurring the NAND will sometimes timeout. This
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is due to both NAND and eMMC controller sharing the same data bus
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on BCMBCA chips. Fix is to extend NAND timeout to allow eMMC
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transactions time to complete.
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Signed-off-by: David Regan <dregan@broadcom.com>
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Reviewed-by: William Zhang <william.zhang@broadcom.com>
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Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
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Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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---
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drivers/mtd/nand/raw/brcmnand/brcmnand.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
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+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
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@@ -101,7 +101,7 @@ struct brcm_nand_dma_desc {
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#define BRCMNAND_MIN_DEVSIZE (4ULL * 1024 * 1024)
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#define NAND_CTRL_RDY (INTFC_CTLR_READY | INTFC_FLASH_READY)
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-#define NAND_POLL_STATUS_TIMEOUT_MS 100
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+#define NAND_POLL_STATUS_TIMEOUT_MS 500
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#define EDU_CMD_WRITE 0x00
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#define EDU_CMD_READ 0x01
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