8f9e91ad03
These patches were generated from: https://github.com/raspberrypi/linux/commits/rpi-6.12.y With the following command: git format-patch -N v6.12.27..HEAD (HEAD -> 8d3206ee456a5ecdf9ddbfd8e5e231e4f0cd716e) Exceptions: - (def)configs patches - github workflows patches - applied & reverted patches - readme patches - wireless patches Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
245 lines
7.4 KiB
Diff
245 lines
7.4 KiB
Diff
From 90bd324fb23dd2f4e8d53a54e12bcd99073e91db Mon Sep 17 00:00:00 2001
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From: Phil Elwell <phil@raspberrypi.com>
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Date: Wed, 26 Mar 2025 15:46:03 +0000
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Subject: [PATCH] overlay: Rework/fix the Pi 5 MIDI UART overlays
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The old Pi 5 MIDI UART overlays replaced the reference to the UART's
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source clock with a fixed clock (essentially an integer dressed up like
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a clock). This is fragile, in that the fixed clock must be updated if
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the source clock's (fixed) frequency is ever changed, but it also relies
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on the source clock having been enabled, which is likely not to be the
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case unless another RP1 UART is being actively used.
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Switching to a fixed-factor-clock solves both of those problems.
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See: https://forums.raspberrypi.com/viewtopic.php?t=385906
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Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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---
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.../dts/overlays/midi-uart0-pi5-overlay.dts | 20 ++++++++++---------
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.../dts/overlays/midi-uart1-pi5-overlay.dts | 20 ++++++++++---------
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.../dts/overlays/midi-uart2-pi5-overlay.dts | 20 ++++++++++---------
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.../dts/overlays/midi-uart3-pi5-overlay.dts | 20 ++++++++++---------
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.../dts/overlays/midi-uart4-pi5-overlay.dts | 20 ++++++++++---------
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5 files changed, 55 insertions(+), 45 deletions(-)
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--- a/arch/arm/boot/dts/overlays/midi-uart0-pi5-overlay.dts
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+++ b/arch/arm/boot/dts/overlays/midi-uart0-pi5-overlay.dts
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@@ -5,23 +5,24 @@
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/*
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* Fake a higher clock rate to get a larger divisor, and thereby a lower
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- * baudrate. The real clock is 50MHz, which we scale so that requesting
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- * 38.4kHz results in an actual 31.25kHz.
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- *
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- * 50000000*38400/31250 = 61440000
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+ * baudrate. Create an intermediary clock that reports the real clock frequency
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+ * multiplied by 38400/31250. This will result in the UART's clock divisor being
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+ * greater by a factor of 38400/31250, such that requesting 38.4kHz results in
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+ * an actual 31.25kHz.
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*/
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/{
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compatible = "brcm,bcm2712";
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fragment@0 {
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- target-path = "/";
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+ target-path = "/clocks";
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__overlay__ {
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- midi_clk: midi_clk0 {
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- compatible = "fixed-clock";
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+ midi_clk: midiclock_0 {
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+ compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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- clock-output-names = "uart0_pclk";
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- clock-frequency = <61440000>;
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+ clocks = <&rp1_clocks RP1_CLK_UART>;
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+ clock-mult = <38400>;
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+ clock-div = <31250>;
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};
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};
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};
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@@ -29,6 +30,7 @@
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fragment@1 {
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target = <&uart0>;
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__overlay__ {
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+ status = "okay";
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clocks = <&midi_clk &rp1_clocks RP1_PLL_SYS_PRI_PH>;
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};
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};
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--- a/arch/arm/boot/dts/overlays/midi-uart1-pi5-overlay.dts
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+++ b/arch/arm/boot/dts/overlays/midi-uart1-pi5-overlay.dts
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@@ -5,23 +5,24 @@
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/*
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* Fake a higher clock rate to get a larger divisor, and thereby a lower
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- * baudrate. The real clock is 50MHz, which we scale so that requesting
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- * 38.4kHz results in an actual 31.25kHz.
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- *
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- * 50000000*38400/31250 = 61440000
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+ * baudrate. Create an intermediary clock that reports the real clock frequency
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+ * multiplied by 38400/31250. This will result in the UART's clock divisor being
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+ * greater by a factor of 38400/31250, such that requesting 38.4kHz results in
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+ * an actual 31.25kHz.
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*/
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/{
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compatible = "brcm,bcm2712";
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fragment@0 {
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- target-path = "/";
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+ target-path = "/clocks";
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__overlay__ {
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- midi_clk: midi_clk1 {
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- compatible = "fixed-clock";
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+ midi_clk: midiclock_1 {
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+ compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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- clock-output-names = "uart1_pclk";
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- clock-frequency = <61440000>;
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+ clocks = <&rp1_clocks RP1_CLK_UART>;
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+ clock-mult = <38400>;
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+ clock-div = <31250>;
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};
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};
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};
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@@ -29,6 +30,7 @@
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fragment@1 {
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target = <&uart1>;
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__overlay__ {
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+ status = "okay";
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clocks = <&midi_clk &rp1_clocks RP1_PLL_SYS_PRI_PH>;
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};
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};
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--- a/arch/arm/boot/dts/overlays/midi-uart2-pi5-overlay.dts
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+++ b/arch/arm/boot/dts/overlays/midi-uart2-pi5-overlay.dts
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@@ -5,23 +5,24 @@
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/*
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* Fake a higher clock rate to get a larger divisor, and thereby a lower
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- * baudrate. The real clock is 50MHz, which we scale so that requesting
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- * 38.4kHz results in an actual 31.25kHz.
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- *
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- * 50000000*38400/31250 = 61440000
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+ * baudrate. Create an intermediary clock that reports the real clock frequency
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+ * multiplied by 38400/31250. This will result in the UART's clock divisor being
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+ * greater by a factor of 38400/31250, such that requesting 38.4kHz results in
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+ * an actual 31.25kHz.
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*/
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/{
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compatible = "brcm,bcm2712";
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fragment@0 {
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- target-path = "/";
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+ target-path = "/clocks";
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__overlay__ {
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- midi_clk: midi_clk2 {
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- compatible = "fixed-clock";
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+ midi_clk: midiclock_2 {
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+ compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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- clock-output-names = "uart2_pclk";
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- clock-frequency = <61440000>;
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+ clocks = <&rp1_clocks RP1_CLK_UART>;
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+ clock-mult = <38400>;
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+ clock-div = <31250>;
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};
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};
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};
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@@ -29,6 +30,7 @@
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fragment@1 {
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target = <&uart2>;
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__overlay__ {
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+ status = "okay";
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clocks = <&midi_clk &rp1_clocks RP1_PLL_SYS_PRI_PH>;
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};
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};
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--- a/arch/arm/boot/dts/overlays/midi-uart3-pi5-overlay.dts
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+++ b/arch/arm/boot/dts/overlays/midi-uart3-pi5-overlay.dts
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@@ -5,23 +5,24 @@
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/*
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* Fake a higher clock rate to get a larger divisor, and thereby a lower
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- * baudrate. The real clock is 50MHz, which we scale so that requesting
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- * 38.4kHz results in an actual 31.25kHz.
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- *
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- * 50000000*38400/31250 = 61440000
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+ * baudrate. Create an intermediary clock that reports the real clock frequency
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+ * multiplied by 38400/31250. This will result in the UART's clock divisor being
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+ * greater by a factor of 38400/31250, such that requesting 38.4kHz results in
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+ * an actual 31.25kHz.
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*/
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/{
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compatible = "brcm,bcm2712";
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fragment@0 {
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- target-path = "/";
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+ target-path = "/clocks";
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__overlay__ {
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- midi_clk: midi_clk3 {
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- compatible = "fixed-clock";
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+ midi_clk: midiclock_3 {
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+ compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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- clock-output-names = "uart3_pclk";
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- clock-frequency = <61440000>;
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+ clocks = <&rp1_clocks RP1_CLK_UART>;
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+ clock-mult = <38400>;
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+ clock-div = <31250>;
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};
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};
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};
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@@ -29,6 +30,7 @@
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fragment@1 {
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target = <&uart3>;
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__overlay__ {
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+ status = "okay";
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clocks = <&midi_clk &rp1_clocks RP1_PLL_SYS_PRI_PH>;
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};
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};
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--- a/arch/arm/boot/dts/overlays/midi-uart4-pi5-overlay.dts
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+++ b/arch/arm/boot/dts/overlays/midi-uart4-pi5-overlay.dts
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@@ -5,23 +5,24 @@
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/*
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* Fake a higher clock rate to get a larger divisor, and thereby a lower
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- * baudrate. The real clock is 50MHz, which we scale so that requesting
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- * 38.4kHz results in an actual 31.25kHz.
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- *
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- * 50000000*38400/31250 = 61440000
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+ * baudrate. Create an intermediary clock that reports the real clock frequency
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+ * multiplied by 38400/31250. This will result in the UART's clock divisor being
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+ * greater by a factor of 38400/31250, such that requesting 38.4kHz results in
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+ * an actual 31.25kHz.
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*/
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/{
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compatible = "brcm,bcm2712";
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fragment@0 {
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- target-path = "/";
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+ target-path = "/clocks";
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__overlay__ {
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- midi_clk: midi_clk4 {
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- compatible = "fixed-clock";
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+ midi_clk: midiclock_4 {
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+ compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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- clock-output-names = "uart4_pclk";
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- clock-frequency = <61440000>;
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+ clocks = <&rp1_clocks RP1_CLK_UART>;
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+ clock-mult = <38400>;
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+ clock-div = <31250>;
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};
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};
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};
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@@ -29,6 +30,7 @@
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fragment@1 {
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target = <&uart4>;
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__overlay__ {
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+ status = "okay";
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clocks = <&midi_clk &rp1_clocks RP1_PLL_SYS_PRI_PH>;
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};
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};
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