8f9e91ad03
These patches were generated from: https://github.com/raspberrypi/linux/commits/rpi-6.12.y With the following command: git format-patch -N v6.12.27..HEAD (HEAD -> 8d3206ee456a5ecdf9ddbfd8e5e231e4f0cd716e) Exceptions: - (def)configs patches - github workflows patches - applied & reverted patches - readme patches - wireless patches Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
183 lines
6 KiB
Diff
183 lines
6 KiB
Diff
From 6c62e56fc0d4e9ac273cee980847a227b77851b6 Mon Sep 17 00:00:00 2001
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From: Stanimir Varbanov <svarbanov@suse.de>
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Date: Mon, 20 Jan 2025 15:01:18 +0200
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Subject: [PATCH] arm64: dts: broadcom: bcm2712: Add PCIe DT nodes
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Add PCIe devicetree nodes, plus needed reset and mip MSI-X
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controllers.
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Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>
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---
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arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 147 ++++++++++++++++++++++
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1 file changed, 147 insertions(+)
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--- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
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+++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
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@@ -192,6 +192,12 @@
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#address-cells = <1>;
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#size-cells = <1>;
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+ pcie_rescal: reset-controller@119500 {
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+ compatible = "brcm,bcm7216-pcie-sata-rescal";
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+ reg = <0x00119500 0x10>;
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+ #reset-cells = <0>;
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+ };
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+
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sdio1: mmc@fff000 {
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compatible = "brcm,bcm2712-sdhci",
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"brcm,sdhci-brcmstb";
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@@ -204,6 +210,12 @@
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mmc-ddr-3_3v;
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};
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+ bcm_reset: reset-controller@1504318 {
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+ compatible = "brcm,brcmstb-reset";
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+ reg = <0x01504318 0x30>;
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+ #reset-cells = <1>;
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+ };
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+
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system_timer: timer@7c003000 {
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compatible = "brcm,bcm2835-system-timer";
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reg = <0x7c003000 0x1000>;
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@@ -431,6 +443,141 @@
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vc4: gpu {
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compatible = "brcm,bcm2712-vc6";
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};
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+
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+ pcie0: pcie@1000100000 {
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+ compatible = "brcm,bcm2712-pcie";
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+ reg = <0x10 0x00100000 0x00 0x9310>;
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+ device_type = "pci";
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+ linux,pci-domain = <0>;
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+ max-link-speed = <2>;
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+ num-lanes = <1>;
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+ #address-cells = <3>;
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+ #interrupt-cells = <1>;
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+ #size-cells = <2>;
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+ interrupt-parent = <&gicv2>;
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+ interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "pcie", "msi";
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+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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+ interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
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+ <0 0 0 2 &gicv2 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
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+ <0 0 0 3 &gicv2 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
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+ <0 0 0 4 &gicv2 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
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+ resets = <&pcie_rescal>, <&bcm_reset 42>;
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+ reset-names = "rescal", "bridge";
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+ msi-controller;
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+ msi-parent = <&pcie0>;
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+
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+ ranges =
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+ /* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
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+ <0x02000000 0x00 0x00000000 0x17 0x00000000 0x00 0xfffffffc>,
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+ /* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */
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+ <0x43000000 0x04 0x00000000 0x14 0x00000000 0x03 0x00000000>;
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+
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+ dma-ranges =
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+ /* 64GiB, 64-bit, prefetchable at PCIe 10_0000_0000 */
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+ <0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>;
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+
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+ status = "disabled";
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+ };
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+
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+ pcie1: pcie@1000110000 {
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+ compatible = "brcm,bcm2712-pcie";
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+ reg = <0x10 0x00110000 0x00 0x9310>;
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+ device_type = "pci";
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+ linux,pci-domain = <1>;
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+ max-link-speed = <2>;
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+ num-lanes = <1>;
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+ #address-cells = <3>;
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+ #interrupt-cells = <1>;
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+ #size-cells = <2>;
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+ interrupt-parent = <&gicv2>;
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+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "pcie", "msi";
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+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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+ interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
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+ <0 0 0 2 &gicv2 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
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+ <0 0 0 3 &gicv2 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
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+ <0 0 0 4 &gicv2 GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
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+ resets = <&pcie_rescal>, <&bcm_reset 43>;
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+ reset-names = "rescal", "bridge";
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+ msi-controller;
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+ msi-parent = <&mip1>;
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+
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+ ranges =
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+ /* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
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+ <0x02000000 0x00 0x00000000 0x1b 0x00000000 0x00 0xfffffffc>,
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+ /* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */
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+ <0x43000000 0x04 0x00000000 0x18 0x00000000 0x03 0x00000000>;
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+
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+ dma-ranges =
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+ /* 64GiB, 64-bit, non-prefetchable at PCIe 10_0000_0000 */
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+ <0x03000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>,
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+ /* 4KiB, 64-bit, non-prefetchable at PCIe ff_ffff_f000 MIP1 */
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+ <0x03000000 0xff 0xfffff000 0x10 0x00131000 0x00 0x00001000>;
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+
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+ status = "disabled";
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+ };
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+
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+ pcie2: pcie@1000120000 {
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+ compatible = "brcm,bcm2712-pcie";
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+ reg = <0x10 0x00120000 0x00 0x9310>;
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+ device_type = "pci";
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+ linux,pci-domain = <2>;
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+ max-link-speed = <2>;
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+ num-lanes = <4>;
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+ #address-cells = <3>;
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+ #interrupt-cells = <1>;
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+ #size-cells = <2>;
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+ interrupt-parent = <&gicv2>;
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+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "pcie", "msi";
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+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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+ interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
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+ <0 0 0 2 &gicv2 GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
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+ <0 0 0 3 &gicv2 GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
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+ <0 0 0 4 &gicv2 GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
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+ resets = <&pcie_rescal>, <&bcm_reset 44>;
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+ reset-names = "rescal", "bridge";
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+ msi-controller;
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+ msi-parent = <&mip0>;
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+
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+ ranges =
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+ /* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
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+ <0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0xfffffffc>,
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+ /* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */
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+ <0x43000000 0x04 0x00000000 0x1c 0x00000000 0x03 0x00000000>;
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+
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+ dma-ranges =
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+ /* 4MiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
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+ <0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0x00400000>,
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+ /* 64GiB, 64-bit, prefetchable at PCIe 10_0000_0000 */
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+ <0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>,
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+ /* 4KiB, 64-bit, non-prefetchable at PCIe ff_ffff_f000 MIP0 */
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+ <0x03000000 0xff 0xfffff000 0x10 0x00130000 0x00 0x00001000>;
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+
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+ status = "disabled";
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+ };
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+
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+ mip0: msi-controller@1000130000 {
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+ compatible = "brcm,bcm2712-mip";
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+ reg = <0x10 0x00130000 0x00 0xc0>,
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+ <0xff 0xfffff000 0x00 0x1000>;
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+ msi-controller;
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+ msi-ranges = <&gicv2 GIC_SPI 128 IRQ_TYPE_EDGE_RISING 64>;
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+ brcm,msi-offset = <0>;
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+ };
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+
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+ mip1: msi-controller@1000131000 {
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+ compatible = "brcm,bcm2712-mip";
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+ reg = <0x10 0x00131000 0x00 0xc0>,
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+ <0xff 0xfffff000 0x00 0x1000>;
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+ msi-controller;
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+ msi-ranges = <&gicv2 GIC_SPI 247 IRQ_TYPE_EDGE_RISING 8>;
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+ brcm,msi-offset = <8>;
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+ };
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};
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timer {
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