8f9e91ad03
These patches were generated from: https://github.com/raspberrypi/linux/commits/rpi-6.12.y With the following command: git format-patch -N v6.12.27..HEAD (HEAD -> 8d3206ee456a5ecdf9ddbfd8e5e231e4f0cd716e) Exceptions: - (def)configs patches - github workflows patches - applied & reverted patches - readme patches - wireless patches Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
89 lines
3.4 KiB
Diff
89 lines
3.4 KiB
Diff
From 693653f118c81b7338ed584bea0bc085b0e8c529 Mon Sep 17 00:00:00 2001
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From: Jonathan Bell <jonathan@raspberrypi.com>
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Date: Thu, 13 Feb 2025 16:46:49 +0000
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Subject: [PATCH] PCI: pcie-brcmstb: optionally extend Tperst_clk time
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Some endpoints need longer than the minimum Tperst_clk time of 100us
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that the PCIe specification allows for, as they may need to sequence
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internal resets off the stable output of internal PLLs prior to removal
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of fundamental reset. PCIe switches are an especially bad case, in some
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cases requiring up to 100 milliseconds for stable downstream link
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behaviour.
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Parse the DT property brcm,tperst-clk-ms and use this to hold PERST# low
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during brcm_pcie_start_link().
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The BRCM RC typically outputs 200us of stable refclk before deasserting
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PERST#. By masking/forcing the output signal while deasserting the
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internal reset, the effect is to extend the length of time that the
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refclk is active and stable before PERST# is released.
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The TX lanes will enter the Polling state before PERST# is released, but
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this appears to be harmless.
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Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
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---
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drivers/pci/controller/pcie-brcmstb.c | 25 ++++++++++++++++++++++++-
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1 file changed, 24 insertions(+), 1 deletion(-)
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--- a/drivers/pci/controller/pcie-brcmstb.c
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+++ b/drivers/pci/controller/pcie-brcmstb.c
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@@ -134,6 +134,7 @@
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PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
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#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
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+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_PERST_ASSERT_MASK 0x8
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#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK 0x200000
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#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
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#define PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x00800000
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@@ -360,6 +361,7 @@ struct brcm_pcie {
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struct subdev_regulators *sr;
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bool ep_wakeup_capable;
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const struct pcie_cfg_data *cfg;
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+ u32 tperst_clk_ms;
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};
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static inline bool is_bmips(const struct brcm_pcie *pcie)
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@@ -1487,13 +1489,32 @@ static int brcm_pcie_start_link(struct b
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u16 nlw, cls, lnksta, tmp16;
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bool ssc_good = false;
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int ret, i;
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+ u32 tmp;
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/* Limit the generation if specified */
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if (pcie->gen)
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brcm_pcie_set_gen(pcie, pcie->gen);
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/* Unassert the fundamental reset */
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- ret = pcie->cfg->perst_set(pcie, 0);
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+ if (pcie->tperst_clk_ms) {
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+ /*
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+ * Increase Tperst_clk time by forcing PERST# output low while
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+ * the internal reset is released, so the PLL generates stable
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+ * refclk output further in advance of PERST# deassertion.
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+ */
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+ tmp = readl(pcie->base + HARD_DEBUG(pcie));
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+ u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_PERST_ASSERT_MASK);
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+ writel(tmp, pcie->base + HARD_DEBUG(pcie));
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+
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+ ret = pcie->cfg->perst_set(pcie, 0);
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+ fsleep(pcie->tperst_clk_ms * USEC_PER_MSEC);
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+
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+ tmp = readl(pcie->base + HARD_DEBUG(pcie));
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+ u32p_replace_bits(&tmp, 0, PCIE_MISC_HARD_PCIE_HARD_DEBUG_PERST_ASSERT_MASK);
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+ writel(tmp, pcie->base + HARD_DEBUG(pcie));
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+ } else {
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+ ret = pcie->cfg->perst_set(pcie, 0);
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+ }
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if (ret)
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return ret;
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@@ -2057,6 +2078,8 @@ static int brcm_pcie_probe(struct platfo
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pcie->ssc = !(pcie->cfg->quirks & CFG_QUIRK_NO_SSC) &&
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of_property_read_bool(np, "brcm,enable-ssc");
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+ of_property_read_u32(np, "brcm,tperst-clk-ms", &pcie->tperst_clk_ms);
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+
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pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal");
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if (IS_ERR(pcie->rescal))
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return PTR_ERR(pcie->rescal);
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