8f9e91ad03
These patches were generated from: https://github.com/raspberrypi/linux/commits/rpi-6.12.y With the following command: git format-patch -N v6.12.27..HEAD (HEAD -> 8d3206ee456a5ecdf9ddbfd8e5e231e4f0cd716e) Exceptions: - (def)configs patches - github workflows patches - applied & reverted patches - readme patches - wireless patches Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
49 lines
1.7 KiB
Diff
49 lines
1.7 KiB
Diff
From 90500343a3eb36d4ed374b2ec2163a5210c38939 Mon Sep 17 00:00:00 2001
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From: Jonathan Bell <jonathan@raspberrypi.com>
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Date: Wed, 12 Feb 2025 15:47:08 +0000
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Subject: [PATCH] PCI: brcmstb: Enable CRS software visibility after linkup
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It appears that bits in the Root Control Register are reset with
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perst_n, which means the PCI layer's call to enable CRS prior to
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adding/scanning the bus has no effect. Open-code the enable in
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brcm_pcie_start_link as a workaround.
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Without CRS visibility, configuration reads issued by the CPU don't
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retire if the endpoint returns a CRS response - the RC will poll until a
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(large) timeout is reached. This means the core can stall for a long
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time during boot.
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Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
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---
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drivers/pci/controller/pcie-brcmstb.c | 13 ++++++++++++-
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1 file changed, 12 insertions(+), 1 deletion(-)
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--- a/drivers/pci/controller/pcie-brcmstb.c
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+++ b/drivers/pci/controller/pcie-brcmstb.c
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@@ -1358,7 +1358,7 @@ static int brcm_pcie_start_link(struct b
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{
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struct device *dev = pcie->dev;
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void __iomem *base = pcie->base;
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- u16 nlw, cls, lnksta;
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+ u16 nlw, cls, lnksta, tmp16;
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bool ssc_good = false;
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int ret, i;
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@@ -1407,6 +1407,17 @@ static int brcm_pcie_start_link(struct b
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pci_speed_string(pcie_link_speed[cls]), nlw,
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ssc_good ? "(SSC)" : "(!SSC)");
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+ /*
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+ * RootCtl bits are reset by perst_n, which undoes pci_enable_crs()
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+ * called prior to pci_add_new_bus() during probe. Re-enable here.
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+ */
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+ tmp16 = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_RTCAP);
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+ if (tmp16 & PCI_EXP_RTCAP_CRSVIS) {
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+ tmp16 = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_RTCTL);
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+ u16p_replace_bits(&tmp16, 1, PCI_EXP_RTCTL_CRSSVE);
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+ writew(tmp16, base + BRCM_PCIE_CAP_REGS + PCI_EXP_RTCTL);
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+ }
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+
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return 0;
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}
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